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ksz8462hl/ksz8462fhl ieee 1588 precision time protocol - enabled two - port 10/100mb/s ethernet switch with 8 or 16 bit host interface revision 1.0 ethersynch and linkmd are trademark s of micrel, inc . magic packet is a trademark of advanced micro devices, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com june 11, 2014 revision 1.0 general description the ksz8462 ethersynch ? product line consists of ieee 1588v2 - enabled ethernet switches, providing integrated communications and synchronization for a range of i ndustrial ethernet applications. the ksz8462 ethersynch product enables distributed, daisy?chained topologies preferred for industrial ethernet networks. conventional centralized (i.e., star?wired) topologies are also supported for dual?homed, fault tolera nt arrangements. a flexible 8 - or 16?bit general bus interface is provided for interfacing to an external host processor. the ksz8462 devices incorporate the ieee 1588v2 protocol. sub - microsecond synchronization is available via the use of hardware based time stamping and transparent clocks making it the ideal solution for time synchronized layer 2 communication in critical industrial applications. extensive general purpose i/o (gpio) capabilities are available to use with the ieee 1588v2 ptp to efficientl y and accurately interface to locally - connected devices. complementing the industrys most - integrated ieee 1588v2 device is a precision timing protocol (ptp) v2 software stack that has been pre?qualified with the ksz84xx product family. the ptp stack has b een optimized around the ksz84xx chip architecture, and is available in source code format along with micrels chip driver. the wire?speed, store?and?forward switching fabric provides a full complement of quality - of -s ervice (qos) and congestion control fea tures optimized for real?time ethernet. ethersynch? the ksz8462 product is built upon micrels industry ? leading ethernet technology, with features designed to offload host processing and streamline your overall design: ? wire?speed ethernet switching fabric with extensive filtering ? two integrated 10/100 base - tx phy t ransceivers , featuring the industrys lowest power consumption ? full? featured qos support ? flexible management options that support common standard interfaces a robust assortment of power - management features including energy -e fficient ethernet (eee) have bee n designed in to satisfy energy - efficient environments. datasheets and support documentation are available on micrels web site at: www.micrel.com . ksz8462 top level architecture downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 2 revision 1.0 functional diagram ksz8462hl/ksz8462fhl functional diagram downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 3 revision 1.0 features management capabilities ? the ksz8462 includes all the functions of a 10/100 base ?t/tx/fx switch system which combines a switch engine, frame buffer management, address look - up table, queue management, mib counters, media access controllers (mac) and phy tran sceivers ? no n ? blocking store ? and ? forward switch fabric assures fast packet delivery by utilizing 1024 entry forwarding table ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port ? mib counters for fully - compliant statistics gathering ? 34 counters per port ? loopback modes for remote failure diagnostics ? rapid spanning tree protocol support (rstp) for topology management and ring/linear recovery robust phy ports ? two integrated ieee 802.3/802. 3u compliant ethernet transceivers supporting 10 base - t and 100 base - tx ? copper and 100 base - fx fiber mode support in the ksz8462fhl ? copper mode support in the ksz8462hl ? on?chip termination resistors and internal biasing for differential pairs to reduce power ? hp auto mdi/mdi?x crossover support eliminating the need to differentiate between straight or crossover cables in applications mac ports ? three internal media access control (mac) units ? 2kb yte jumbo packet support ? tail tagging mode (one byte added before fcs) s upport at port 3 to inform the processor which ingress port receives the packet and its priority ? programmable mac addresses for port 1 and port 2 and self ? address filtering support ? mac filtering function to filter or forward unknown u nicast packets ? port 1 and port 2 macs programmable as either end - to - end ( e2e ) or peer - to - peer ( p2p ) transparent clock (tc) ports for 1588 support advanced switch capabilities ? non ? blocking store ? and ? forward switch fabric assures fast packet delivery by utilizing 1024 entry forwarding table ? ieee 802.1q vlan for up to 16 groups with full range of vlan ids ? ieee 802.1p/q tag insertion or removal on a per port basis (egress) and support double ? tagging ? vlan id tag/untag options on per port basis ? fully compliant with ieee 802.3/802. 3u standards ? ieee 802.3x full ? duplex wit h force mode option and half ? duplex backpressure collision flow control ? ieee 802.1 w rapid spanning tree protocol support ? igmp v1/v2/v3 snooping for multicast packet filtering ? qos/cos packets prioritization support: 802.1p, diffserv ? based and re ? mapping of 802.1p priority field per port basis on four priority levels ipv4/ipv6 qos support ? ip v 6 m ulticast l istener d iscovery (mld) snooping support ? programmable rate limiting at the ingress and egress ports ? broadcast storm protection ? 1k entry forwarding table with 32k frame buffer ? 4 priority queues with dynamic packet mapping for ieee 802.1p, ipv4 tos (diffserv), ipv6 traffic class, etc. ? source address filtering for implementing ring topologies comprehensive configuration registers access ? complete register access via the parallel host i nterface ? facility to load mac address from eeprom at power - up and reset time ? i/o pin strapping facility to set certain register bits from i/o pins at reset time ? control registers configurable on ? the ? fly downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 4 revision 1.0 ieee 1588v2 ptp and clock synchronization ? fully compliant with the ieee 1588v2 precision time protocol ? one ? step or two ? step transparent c lock (tc) timing corrections ? e nd - to - end (e2e) or peer - to - peer ( p2p ) transparent clock ( tc ) ? grandmaster, m aster , s lave , and o rdin ary c lock (oc) s upport ? ieee1588v2 ptp m ulticast and u nicast frame support ? transports of ptp over ipv4/ipv6 udp and ieee 802.3 ethernet ? delay request ? response and peer delay mechanism ? ingress/e gress packet timestamp capture/recording and checksum u pdate ? correction field u pd ate with residence time and link delay ? ieee1588v2 ptp packet filtering unit to reduce host processor overhead ? a 64 - bit adjustable system precision clock ? 12 trigger output u nits and 12 timestamp input units available for flexible ieee1588v2 control of 7 programmable gpio[6:0] pins synchronized to the precision time clock ? gpio pin usage for 1 pps generation, frequency generator, control bit streams, event monitoring, precision pulse generation, complex waveform generation host inter face ? selectable 8 - or 16 - bit wide interface ? supports b ig - and l ittle - endian processors ? indirect data bus for data, address and byte enable to access any i/o registers and rx/tx fifo buffers ? large internal memory with 12kbyte for rx fifo and 6kbytes for tx fifo ? programmable low, high and overrun water mark for flow control in rx fifo ? efficient architecture design with configurable host interrupt schemes to minimize host cpu overhead and utilization ? queue management unit (qmu) supervises data transfers across this interface power and power management ? single 3.3v power supply with optional vdd i/o for 1.8v, 2.5v or 3.3v ? i ntegrated low voltage ( ~1.3v ) low - noise regulator (ldo) output for digital and analog core power. ? supports ieee p802.3az energy - efficient et hernet ( eee ) to reduce power consumption in transceivers in lpi state ? full?chip hardware or software power down (all registers value are not saved and strap ? in value will re ? strap after release the power down) ? energy d etect p ower d own (ed pd ), which disables the phy transceiver when cables are removed ? wake - on - lan supported with configurable packet control ? dynamic clock tree control to reduce clocking in areas not in use ? power consumption less than 0.5w additional features ? single 25mhz 50ppm reference clock requirement ? comprehensive programmable two led indicators support for link, activity, full/half duplex and 10/100 speed ? led pins directly controllable ? industrial temperature r ange: C 40 o c to +85 o c ? 64 - pin, 10mm 10mm, lead free, rohs, lqfp package ? 0 .11 m technology for lower power consumption applications ? industrial ethernet applications that employ ieee 802.3 - compliant macs. (ethernet/ip, profinet, modbus tcp, etc) ? real?time ethernet networks requiring sub?microsecond synchronization over standard e thernet ? iec 61850 networks supporting power substation automation ? networked measurement and control systems ? industrial automation and motion control systems ? test and measurement equipment downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 5 revision 1.0 ordering information part number temperature range package lead finish description ksz8462hli ? 40 c to +85 c 64?pin lqfp pb?free industrial temperature device with generic host interface ksz8462f h li ? 40 c to +85 c 64?pin lqfp pb?free industrial temperature device with generic host interface and fiber (100 base- fx) support ksz8462hli -eval evaluation board with ksz8462hli. also supports the KSZ8462FHLI. revision history revision date summary of changes 1.0 6/11 /14 initial release of ksz8462hl/fhl product datasheet. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 6 revision 1.0 contents general description ................................................................................................................................................................ 1 functional diagram ................................................................................................................................................................ . 2 features .................................................................................................................................................................................. 3 management capabilit ies .................................................................................................................................................... 3 robust phy ports ............................................................................................................................................................... 3 mac ports ........................................................................................................................................................................... 3 advanced switch capa bilities ............................................................................................................................................. 3 ipv4/ipv6 qos support ........................................................................................................................................................ 3 comprehensive configuration registers access ................................................................................................................ 3 ieee 1588v2 ptp and clock synchronization .................................................................................................................... 4 host interface ...................................................................................................................................................................... 4 power and power management .......................................................................................................................................... 4 additional features .............................................................................................................................................................. 4 applications ............................................................................................................................................................................. 4 ordering information ............................................................................................................................................................... 5 revision history ...................................................................................................................................................................... 5 contents .................................................................................................................................................................................. 6 acronyms .............................................................................................................................................................................. 20 pin configuration ................................................................................................................................................................... 23 pin descri ption ...................................................................................................................................................................... 24 strapping options ................................................................................................................................................................ . 29 functional description ........................................................................................................................................................... 30 direction terminology ........................................................................................................................................................... 30 physical (phy) block ............................................................................................................................................................ 31 100base? tx transmit ..................................................................................................................................................... 31 100base?tx receive ...................................................................................................................................................... 31 scrambler/de?scrambler (100base?tx only) ................................................................................................................ 31 pll clock synthesizer (recovery) .................................................................................................................................... 31 100base?fx operation ................................................................................................................................................... 31 100base?fx signal detection ......................................................................................................................................... 32 100base?fx far?end fault ............................................................................................................................................ 32 10base?t transmit .......................................................................................................................................................... 32 10base?t r eceive ........................................................................................................................................................... 32 mdi/mdi?x auto crossover .............................................................................................................................................. 32 straight cable ................................................................................................................................................................ 33 crossover cable ............................................................................................................................................................ 33 auto?negotiation ............................................................................................................................................................... 34 linkmd ? cabl e diagnostics ............................................................................................................................................... 35 access ............................................................................................................................................................................ 35 usage ............................................................................................................................................................................. 35 on?chip termination resistors ........................................................................................................................................ 35 loopback support ............................................................................................................................................................. 35 far?end loopback ......................................................................................................................................................... 36 near?end (remote) loopback ...................................................................................................................................... 36 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 7 revision 1.0 media access controller (mac) block .................................................................................................................................. 37 mac operation .................................................................................................................................................................. 37 address lookup ................................................................................................................................................................ . 37 learning ............................................................................................................................................................................. 37 migration ............................................................................................................................................................................ 37 aging .................................................................................................................................................................................. 37 forwarding ......................................................................................................................................................................... 37 inter packet gap (ipg) ...................................................................................................................................................... 40 back?off algorithm ............................................................................................................................................................ 40 late collision ..................................................................................................................................................................... 40 legal packet size .............................................................................................................................................................. 40 flow control ....................................................................................................................................................................... 40 half?duplex backpressure ................................................................................................................................................ 40 broadcast storm protection ............................................................................................................................................... 41 port individual mac address and source port filtering ................................................................................................... 41 address filtering function ................................................................................................................................................. 41 switch block .......................................................................................................................................................................... 43 switching engine ............................................................................................................................................................... 43 spanning tree support ..................................................................................................................................................... 43 rapid spanning tree support ........................................................................................................................................... 44 discarding state ............................................................................................................................................................. 44 learning state ................................................................................................................................................................ 44 forwarding sta te ............................................................................................................................................................ 44 tail tagging mode ............................................................................................................................................................. 44 igmp support .................................................................................................................................................................... 45 igmp snooping ........................................................................................................................................................... 45 multicast address insertion in the static mac table .................................................................................................. 45 ipv6 mld snooping ....................................................................................................................................................... 45 port mirroring support ....................................................................................................................................................... 46 receive only mirror - on -a- port .................................................................................................................................... 46 transmit only mirror - on -a- port ................................................................................................................................... 46 receive and transmit mirror - on - two - ports ................................................................................................................ 46 ieee 802.1q vlan support .............................................................................................................................................. 46 qos priority support .......................................................................................................................................................... 47 port?based priority ............................................................................................................................................................ 47 802.1p?based priority ....................................................................................................................................................... 47 802.1p priority field re?mapping ..................................................................................................................................... 48 diffserv - based priority ...................................................................................................................................................... 48 rate - limiting support ........................................................................................................................................................ 49 mac address filtering function ........................................................................................................................................ 49 queue management unit (qmu) .......................................................................................................................................... 50 transmit queue (txq) frame format .............................................................................................................................. 50 frame transmitting path operation in txq ...................................................................................................................... 51 driver routine for transmitting packets from host processor to ksz8462 ..................................................................... 52 receive queue (rxq) frame format ............................................................................................................................... 53 frame receiving path operation in rxq ......................................................................................................................... 53 driver routine for receiving packets from the ksz8462 to the host processor ............................................................. 54 ieee 1588 precision time protocol (ptp) block .................................................................................................................. 56 ieee 1588 ptp clock types ............................................................................................................................................. 57 ie ee 1588 ptp one?step or two?step clock operation ............................................................................................... 57 ieee 1588 ptp best master clock selection ................................................................................................................... 57 ieee 1588 ptp system time clock ................................................................................................................................ . 57 updating the system time clock .................................................................................................................................... 59 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 8 revision 1.0 ieee 1588 ptp message processing ............................................................................................................................... 60 ieee 1588 ptp ingress packet processing .................................................................................................................. 60 ieee 1588 ptp egress packet processing ................................................................................................................... 60 ieee 1588 ptp event triggering and timestamping ....................................................................................................... 61 ieee 1588 ptp trigger outputs ....................................................................................................................................... 61 ieee 1588 ptp event timestamp input ........................................................................................................................... 61 ieee 1588 ptp event interrupts ....................................................................................................................................... 62 ieee 1588 gpio ............................................................................................................................................................... 62 general purpose and ieee 1588 input/output (gpio) ........................................................................................................ 63 overview ............................................................................................................................................................................ 63 gpio pin functionality control .......................................................................................................................................... 63 gpio pin control register layout ..................................................................................................................................... 64 gpio trigger output units and timestamp input unit interrupts ..................................................................................... 67 using the gpio pins with the trigger output units .......................................................................................................... 68 creating a low?going pulse at a specific time ........................................................................................................... 68 creating a high?going pulse at a specific time .......................................................................................................... 68 creating a free running clock source ......................................................................................................................... 69 creating finite length periodic bit streams at a specific time .................................................................................... 70 creating finite length non?uniform bit streams at a specific time ............................................................................ 70 creating complex waveforms at a specific time ......................................................................................................... 71 using the gpio pins with the timestamp input units ....................................................................................................... 72 timestamp value ........................................................................................................................................................... 72 timestamping an incoming low?going edge ............................................................................................................... 72 timestamping an incoming high?going edge .............................................................................................................. 73 device clocks ........................................................................................................................................................................ 74 gpio and ieee 1588 related clocking ............................................................................................................................ 74 power .................................................................................................................................................................................... 75 power management .............................................................................................................................................................. 77 normal operation mode .................................................................................................................................................... 77 energy detect mode .......................................................................................................................................................... 77 global soft power - down mode ......................................................................................................................................... 78 energy - efficient ethernet (eee) ........................................................................................................................................ 78 transmit direction control for mii mode ........................................................................................................................ 79 receive direction control for mii mode ......................................................................................................................... 79 wake - on - lan ................................................................................................................................................................... 80 detection of ene rgy ........................................................................................................................................................... 80 detection of linkup ............................................................................................................................................................ 80 wake?up packet ............................................................................................................................................................... 80 magic packet? ................................................................................................................................................................ . 80 interrupt generation on power management related events .......................................................................................... 81 to generate an interrupt on the pme signal pin .......................................................................................................... 81 to generate an interrupt on the intrn signal pin ....................................................................................................... 81 interfaces ............................................................................................................................................................................... 82 bus interface unit (biu) / host interface ........................................................................................................................... 82 supported transfers ...................................................................................................................................................... 82 physical data bus size .................................................................................................................................................. 82 little and big endian support ........................................................................................................................................ 83 asynchronous interface ................................................................................................................................................. 83 biu summary ................................................................................................................................................................ . 84 serial eeprom interface .................................................................................................................................................. 85 device registers ................................................................................................................................................................... 86 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 9 revision 1.0 register map of cpu accessible i/o registers .................................................................................................................... 88 i/o registers ...................................................................................................................................................................... 88 internal i/o r egister space mapping for switch control and configuration (0x000 C 0x0ff) ...................................... 88 internal i/o register space mapping for host interface unit (0x100 C 0x16f) ............................................................. 94 internal i/o register space mapping for the qmu (0x170 ? 0x1ff) ............................................................................ 96 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) ............................................ 98 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) ............................ 107 internal i/o register space mapping for ptp 1588 clock and global control (0x600 C 0x7ff) ............................... 119 register bit d efinitions ........................................................................................................................................................ 122 internal i/o register mapping for switch control and configuration (0x000 ? 0x0ff) ................................................... 122 chip id and enable register (0x00 ? 0x001): cider ..................................................................................................... 122 switch global control register 1 (0x002 ? 0x003): sgcr1 ........................................................................................... 122 switch global control register 2 (0x004 C 0x00 5): sgcr2 ........................................................................................... 124 switch global control register 3 (0x006 C 0x007): sgcr3 ........................................................................................... 125 0x008 C 0x00b: reserved ............................................................................................................................................... 125 swit ch global control register 6 (0x00c C 0x00d): sgcr6 .......................................................................................... 126 switch global control register 7 (0x00e C 0x00f): sgcr7 .......................................................................................... 127 mac address register 1 (0x010 C 0x011): macar1 ..................................................................................................... 128 mac address register 2 (0x012 C 0x013): macar2 ..................................................................................................... 128 mac address register 3 (0x014 C 0x015): macar3 ..................................................................................................... 128 type - of - service (tos) priority control registers ............................................................................................................... 129 tos priority control register 1 (0x016 C 0x017): tosr1 .............................................................................................. 129 tos priority control register 2 (0x018 C 0x019): tosr2 .............................................................................................. 130 tos priority control register 3 (0x01a C 0x01b): tosr3 ............................................................................................. 131 tos priority control register 4 (0x01c C 0x1d): tosr4 .............................................................................................. 131 tos priority control register 5 (0x01e C 0x1 f): tosr5 ............................................................................................... 132 tos priority control register 6 (0x020 C 0x021): tosr6 .............................................................................................. 133 tos priority control register 7 (0x022 C 0x023): tosr7 .............................................................................................. 133 tos priority control register 8 (0x024 C 0x025): tosr8 .............................................................................................. 134 indirect access data registers ........................................................................................................................................... 135 indirect access data register 1 (0x026 C 0x027): iadr1 .............................................................................................. 135 indirect access data register 2 (0x028 C 0x029): iadr2 .............................................................................................. 135 indirect access data register 3 (0x02a C 0x02b): iadr3 ............................................................................................. 135 indirect access data register 4 (0x02c C 0x02d): iadr4 ............................................................................................. 135 indirect access data register 5 (0x02e C 0 x02f): iadr5 .............................................................................................. 136 indirect access control register (0x030 C 0x031): iacr ............................................................................................... 136 power management control and wake - up event status ................................................................................................... 137 power management control and wake?up event status (0x032 C 0x033): pmctrl .................................................. 137 power management event enable register (0x034 C 0x035): pmee ............................................................................ 138 go sleep time and clock tree power - down control registers ........................................................................................ 139 go sleep time register (0x036 C 0x037): gst .............................................................................................................. 139 clock tree power - down control register (0x038 C 0x039): ctpdc ............................................................................. 139 0x03a C 0x04b: reserved ............................................................................................................................................... 139 phy and mii basic control registers ................................................................................................................................ . 140 phy 1 and mii basic control register (0x04c C 0x04d): p1mbcr ............................................................................... 140 phy 1 and mii basic status register (0x04e C 0x04f): p1mbsr ................................................................................. 141 phy 1 phyid low register (0x050 C 0x051): phy1ilr ................................................................................................ 14 2 phy 1 phyid high register (0x052 C 0x053): p hy1ihr .............................................................................................. 142 phy 1 auto?negotiation advertisement register (0x054 C 0x055): p1anar ............................................................... 143 phy 1 auto?negotiation link partner ability register (0x056 C 0x057): p1anlpr ...................................................... 144 phy 2 and mii basic control register (0x058 C 0x059): p2mbcr ................................................................................ 144 phy 2 and mii basic status register (0x05a C 0x05b): p2mbsr ................................................................................. 146 phy 2 phyid low register (0x05c C 0x05d): phy2ilr ............................................................................................... 147 phy 2 phyid high register (0x05e C 0x05f): phy2ihr .............................................................................................. 147 phy 2 auto?negotiation advertisement register (0x060 C 0x061): p2anar ............................................................... 147 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 10 revision 1.0 phy 2 auto?negotiation link partner ability register (0x062 C 0x063): p2anlpr ...................................................... 148 0x0x064 C 0x065: reserved ............................................................................................................................................ 148 phy1 special control and status register (0x066 C 0x067): p1phyctrl .................................................................. 149 0x068 C 0x069: reserved ................................................................................................................................................ 149 phy 2 special control and status register (0x06a C 0x06b): p2phyctrl ................................................................ . 149 port 1 control registers ...................................................................................................................................................... 150 port 1 control register 1 (0x06c C 0x06d): p1cr1 ....................................................................................................... 150 port 1 control register 2 (0x06e C 0x06f): p1cr2 ........................................................................................................ 152 port 1 vid control register (0x070 C 0x071): p1vidcr ................................................................................................ 153 port 1 control register 3 (0x072 C 0x073): p1cr3 ........................................................................................................ 153 port 1 ingress rate control register 0 (0x074 C 0x 075): p1ircr0 ............................................................................... 154 port 1 ingress rate control register 1 (0x076 C 0x077): p1ircr1 ............................................................................... 155 port 1 egress rate control register 0 (0x078 C 0x079): p1ercr0 .............................................................................. 155 port 1 egress rate control register 1 (0x07a C 0x07b): p1ercr1 ............................................................................. 155 port 1 phy special control/status, linkmd (0x07c C 0x07d): p1scslmd .................................................................. 156 port 1 control register 4 (0x07e C 0x07f): p1cr4 ........................................................................................................ 157 port 1 status register (0x080 C 0x081): p1sr ............................................................................................................... 158 0x082 C 0x083: reserved ................................................................................................................................................ 159 port 2 control registers ...................................................................................................................................................... 160 po rt 2 control register 1 (0x084 C 0x085): p2cr1 ........................................................................................................ 160 port 2 control register 2 (0x086 C 0x087): p2cr2 ........................................................................................................ 162 port 2 vid control register (0x088 C 0x089): p2vidcr ................................................................................................ 163 port 2 control register 3 (0x08a C 0x08b): p2cr3 ....................................................................................................... 163 port 2 ingress rate control register 0 (0x08c C 0x08d): p2ircr0 .............................................................................. 164 port 2 ingress rate control register 1 (0x08e C 0x08f): p2ircr1 .............................................................................. 164 port 2 egress rate control register 0 (0x090 C 0x091): p2ercr0 .............................................................................. 165 port 2 egress rate control register 1 (0x092 C 0x093): p2ercr1 .............................................................................. 165 port 2 phy special control/status, linkmd (0x094 C 0x095): p2scslmd ................................................................... 166 port 2 control register 4 (0x096 C 0x097): p2cr4 ........................................................................................................ 167 port 2 status register (0x098 C 0x099): p2sr ............................................................................................................... 169 0x09a C 0x09b: reserved ............................................................................................................................................... 170 port 3 control registers ...................................................................................................................................................... 171 port 3 control register 1 (0x09c C 0x09d): p3cr1 ....................................................................................................... 171 port 3 control register 2 (0x09e C 0x09f): p3cr2 ........................................................................................................ 172 port 3 vid control register (0x0a0 C 0x0a1): p3vidcr ............................................................................................... 173 port 3 control register 3 (0x0a2 C 0x0a3): p3cr3 ....................................................................................................... 174 port 3 ingress rate control register 0 (0x0a4 C 0x 0a5): p3ircr0 .............................................................................. 174 port 3 ingress rate control register 1 (0x0a6 C 0x0a7): p3ircr1 .............................................................................. 175 port 3 egress rate control register 0 (0x0a8 C 0x0a9): p3ercr0 ............................................................................. 175 port 3 egress rate control register 1 (0x0aa C 0x0ab): p3ercr1 ............................................................................. 175 switch global control regi sters ......................................................................................................................................... 176 switch global control register 8 (0x0ac C 0x0ad): sgcr8 ......................................................................................... 176 switch global control register 9 (0x0ae C 0x0af): sgcr9 ......................................................................................... 177 source address filtering registers .................................................................................................................................... 178 source address filtering mac address 1 register low (0x0b0 C 0x0b1): safmaca1l ............................................. 178 source address filtering mac address 1 register middle (0x0b2 C 0x0b3): safmaca1m ........................................ 178 source address filtering mac address 1 register high (0x0b4 C 0x0b5): safmaca1h ............................................ 178 source address filtering mac address 2 register low (0x0b6 C 0x0b7): safmaca2l ............................................. 178 source address filtering mac address 2 register middle (0x0b8 C 0x0b9): safmaca2m ........................................ 178 source address filtering mac address 2 register high (0x0ba C 0x0bb): safmaca2h ........................................... 179 0x0bc C 0x0c7: reserved .............................................................................................................................................. 179 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 11 revision 1.0 txq rate control registers ............................................................................................................................................... 180 port 1 txq rate control register 1 (0x0c8 C 0x0c9): p1txqrcr1 ............................................................................ 180 port 1 txq rate control register 2 (0x0ca C 0x0cb): p1txqrcr2 ........................................................................... 180 port 2 txq rate control register 1 (0x0cc C 0x0cd): p2txqrcr1 ........................................................................... 181 port 2 txq rate control register 2 (0x0ce C 0x0cf): p2txqrcr2 ........................................................................... 181 port 3 txq rate control register 1 (0x0d0 C 0x0d1): p3txqrcr1 ............................................................................ 182 port 3 txq rate control register 2 (0x0d2 C 0x0d3): p3txqrcr2 ............................................................................ 182 0x0d4 C 0x0d5: reserved .............................................................................................................................................. 182 input and output multiplex selection registers .................................................................................................................. 183 input and output multiplex selection register (0x0d6 C 0x0d7): iomxsel .................................................................. 183 configuration status and serial bus mode registers ......................................................................................................... 184 configuration status and seria l bus mode register (0x0d8 C 0x0d9): cfgr .............................................................. 184 0x0da C 0x0db: reserved .............................................................................................................................................. 184 auto - negotiation next page registers ............................................................................................................................... 185 port 1 auto?negotiation next page transmit register (0x0dc C 0x0dd): p1anpt ..................................................... 185 port 1 auto?negotiation link partner received next page register (0x0de C 0x0df): p1alprnp ........................... 186 eee and link partner advertisement registers ................................................................................................................. 187 port 1 eee and link partner advertisement register (0x0e0 C 0x0e1): p1eeea ......................................................... 187 port 1 eee wake error count register (0x0e2 C 0x0e3): p1eeewec ........................................................................ 188 port 1 eee control/status and auto?negotiation expansion register (0x0e4 C 0x0e5): p1eeecs ............................ 188 port 1 lpi recovery time counter register (0x0e6): p1lpirtc .................................................................................. 190 buffer load to lpi control 1 register (0x0e7): bl2lpic1 ............................................................................................. 190 port 2 auto?negotiation next page transmit register (0x0e8 C 0x0e9): p2anpt ....................................................... 190 port 2 auto?negotiation link partner received next page register (0x0ea C 0x0eb): p2alprnp ........................... 191 port 2 eee and link partner advertisement register (0x0ec C 0x0ed): p2eeea ....................................................... 192 port 2 eee wake error count register (0x0ee C 0x0ef): p2eeewec ........................................................................ 193 port 2 eee control/status and auto?negotiation expansion register (0x0f0 C 0x0f1): p2eeecs ............................ 193 port 2 lpi recovery time counter register (0x0 f2): p2lpirtc .................................................................................. 195 pcs eee control register (0x0f3): pcseeec ............................................................................................................. 195 empty txq to lpi wait time control register (0x0f4 C 0x0f5): etlwtc ................................................................... 195 buffer load to lpi control 2 register (0x0f6 C 0x0f7): bl2lpic2 ............................................................................... 196 0x0f8 C 0x0ff: reserved ............................................................................................................................................... 196 internal i/o register space mapping for interrupts, biu, and global reset (0x100 C 0x1ff) ........................................... 197 0x100 C 0x107: reserved ................................................................................................................................................ 197 chip configuration register (0x108 C 0x1 09): ccr ....................................................................................................... 197 0x10a C 0x10f: reserved ............................................................................................................................................... 197 host mac address registers: marl, marm and marh .............................................................................................. 198 host mac address register low (0x110 C 0x111): marl ............................................................................................. 198 host mac address register middle (0x112 C 0x113): marm ........................................................................................ 198 host mac address register high (0x114 C 0x115): marh ........................................................................................... 198 0x116 C 0x121: reserved ................................................................................................................................................ 198 eepr om control register (0x122 C 0x123): eepcr .................................................................................................... 199 memory bist info register (0x124 C 0x125): mbir ....................................................................................................... 199 global reset register (0x126 C 0x127): grr ................................................................................................................ 200 0x128 C 0x129: reserved ................................................................................................................................................ 200 wake - up frame control register (0x12a C 0x12b): wfcr .......................................................................................... 201 0x12c C 0x12f: reserved ............................................................................................................................................... 201 wake - up frame 0 crc0 register (0x130 C 0x131): wf0crc0 ................................................................................... 201 wake - up frame 0 crc1 register (0x132 C 0x133): wf0crc1 ................................................................................... 202 wake - up frame 0 byte mask 0 register (0x134 C 0x135): wf0bm0 ............................................................................ 202 wake - up frame 0 byte mask 1 register (0x136 C 0x137): wf0bm1 ............................................................................ 202 wake - up frame 0 byte mask 2 register (0x138 C 0x139): wf0bm2 ............................................................................ 202 wake - up frame 0 byte mask 3 register (0x13a C 0x13b): wf0bm3 ........................................................................... 202 0x13c C 0x13f: reserved ............................................................................................................................................... 203 wake - up frame 1 crc0 register (0x140 C 0x141): wf1crc0 ................................................................................... 203 wake - up frame 1 crc1 register (0x142 C 0x143): wf1crc1 ................................................................................... 203 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 12 revision 1.0 wake - up frame 1 byte mask 0 register (0x144 C 0x145): wf1bm0 ............................................................................ 203 wake - up frame 1 byte mask 1 register (0x146 C 0x147): wf1bm1 ............................................................................ 203 wake - up frame 1 byte mask 2 register (0x148 C 0x149): wf1bm2 ............................................................................ 204 wake - up frame 1 byte mask 3 register (0x14a C 0x14b): wf1bm3 ........................................................................... 204 0x14c C 0x14f: reserved ............................................................................................................................................... 204 wake - up frame 2 crc0 register (0x150 C 0x151): wf2crc0 ................................................................................... 204 wake - up frame 2 crc1 register (0x152 C 0x153): wf2crc1 ................................................................................... 204 wake - up frame 2 byte mask 0 register (0x154 C 0x155): wf2bm0 ............................................................................ 205 wake - up frame 2 byte mask 1 register (0x156 C 0x157): wf2bm1 ............................................................................ 205 wake - up frame 2 byte mask 2 register (0x158 C 0x159): wf2bm2 ............................................................................ 205 wake - up frame 2 byte mask 3 register (0x15a C 0x15b): wf2bm3 ........................................................................... 205 0x15c C 0x15f: reserved ............................................................................................................................................... 205 wake - up frame 3 crc0 register (0x160 C 0x161): wf3crc0 ................................................................................... 206 wake - up frame 3 crc1 register (0x162 C 0x163): wf3crc1 ................................................................................... 206 wake - up frame 3 byte mask 0 register (0x164 C 0x165): wf3bm0 ............................................................................ 206 wake - up frame 3 byte mask 1 register (0x166 C 0x167): wf3bm1 ............................................................................ 206 wake - up frame 3 byte mask 2 register (0x168 C 0x169): wf3bm2 ............................................................................ 206 wake - up frame 3 byte mask 3 register (0x16a C 0x16b): wf3bm3 ........................................................................... 207 0x16c C 0x16f: reserved ............................................................................................................................................... 207 internal i/o register space mapping for the queue management unit (qmu) (0x170 C 0x1ff) ...................................... 208 transmit control register (0x170 C 0x171): txcr ......................................................................................................... 208 transmit status register (0x172 C 0x173): txsr .......................................................................................................... 209 receive control register 1 (0x174 C 0x175): rxcr1 .................................................................................................... 209 receive control register 2 (0x176 C 0x177): rxcr2 .................................................................................................... 210 txq memory information register (0x178 C 0x179): txmir ......................................................................................... 211 0x17a C 0x17b: reserved ............................................................................................................................................... 211 receive frame header status register (0x17c C 0x17d): rxfhsr ............................................................................ 211 receive frame header byte count register (0x17e C 0x17f): rxfhbcr ................................................................... 212 txq command register (0x180 C 0x181): txqcr ....................................................................................................... 213 rxq command register (0x182 C 0x183): rxqcr ....................................................................................................... 213 tx frame data pointer register (0x184 C 0x185): txfdpr ......................................................................................... 214 rx frame data pointer register (0x186 C 0x187): rxfdpr ......................................................................................... 215 0x188 C 0x18b: reserved ............................................................................................................................................... 215 rx duration timer threshold register (0x18c C 0x18d): rxdttr .............................................................................. 215 rx data byte count threshold register (0x18e C 0x18f): rxdbctr ......................................................................... 216 internal i/o register space mapping for interrupt registers (0x190 C 0x193) ................................................................... 217 interrupt enable register (0x190 C 0x191): ier ............................................................................................................. 217 interrupt status register (0x192 C 0x193): isr .............................................................................................................. 218 0x194 C 0x19b: reserved ............................................................................................................................................... 219 inte rnal i/o register space mapping for the queue management unit (qmu) (0x19c C 0x1b9) ..................................... 220 rx frame count and threshold register (0x1 9c C 0x19d): rxfctr .......................................................................... 220 tx next total frames size register (0x19e C 0x19f): txntfsr ................................................................................ 220 mac address hash table register 0 (0x1a0 C 0x1a1): mahtr0 ................................................................................. 220 multicast table register 0 ........................................................................................................................................... 220 mac address hash table register 1 (0x1a2 C 0x1a3): mahtr1 ................................................................................. 221 multicast table register 1 ........................................................................................................................................... 221 mac address hash table register 2 (0x1a4 C 0x1a5): mahtr2 ................................................................................. 221 multicast table register 2 ........................................................................................................................................... 221 mac address hash table register 3 (0x1a6 C 0x1a7): mahtr3 ................................................................................. 221 multicast table register 3 ........................................................................................................................................... 221 0x1a8 C 0x1af: reserved ............................................................................................................................................... 221 flow control low water mark register (0x1b0 C 0x1b1): fclwr ................................................................................ 221 flow control high water mark register (0x1b2 C 0x1b3): fchwr .............................................................................. 222 flow control overrun water mark register (0x1b4 C 0x1b5): fcowr ........................................................................ 222 rx frame count register (0x1b8 C 0x1b9): rxfc ....................................................................................................... 222 0x1ba C 0x1ff: reserved .............................................................................................................................................. 2 22 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 13 revision 1.0 inte rnal i/o register space mapping for trigger output units (12 units, 0x200 C 0x3ff) ................................................ 223 trigger error register (0x200 C 0x201): tr ig_err ...................................................................................................... 223 trigger active register (0x202 C 0x203): trig_active ............................................................................................... 223 trigger done register (0x204 C 0x205): trig_done ................................................................................................... 223 trigger enable register (0x206 C 0x207): trig_en ...................................................................................................... 224 trigger software reset register (0x208 C 0x209): trig_sw_rst .............................................................................. 224 trigger output unit 12 output pps pulse width register (0x20a C 0x20b): trig12_pps_width ............................ 224 0x20c C 0x21f: reserved ............................................................................................................................................... 224 trigger output unit 1 target time in nanoseconds low?word register (0x220 C 0x221): trig1_tgt_nsl ............ 225 trigger output unit 1 target time in nanoseconds high?word register (0x222 C 0x223): trig1_tgt_nsh ........... 225 trigger output unit 1 target time in seconds low?word register (0x224 C 0x225): trig1_tgt_sl ....................... 225 trigger output unit 1 target time in seconds high?word register (0x226 C 0x227): trig1_tgt_sh ...................... 225 trigger output unit 1 configuration and control register 1 (0x228 C 0x229): trig1_cfg_1 ...................................... 226 trigger output unit 1 configuration and control register 2 (0x22a C 0x22b): trig1_cfg_2 ..................................... 228 trigger output unit 1 configuration and control register 3 (0x22c C 0x22d): trig1_cfg_3 .................................... 228 trigger output unit 1 configuration and control register 4 (0x22e C 0x22f): trig1_cfg_4 ..................................... 228 trigger output unit 1 configuration and control register 5 (0x230 C 0x231): trig1_cfg_5 ...................................... 228 trigger output unit 1 configuration and control register 6 (0x232 C 0x233): trig1_cfg_6 ...................................... 229 trigger output unit 1 configuration and control register 7 (0x234 C 0x235): trig1_cfg_7 ...................................... 229 trigger output unit 1 configuration and control register 8 (0x236 C 0x237): trig1_cfg_8 ...................................... 229 0x238 C 0x23f: reserved ............................................................................................................................................... 229 trigger output unit 2 target time and output configuration/control registers (0x240 C 0x257) ................................ . 230 trigger output unit 2 configuration and control register 1 (0x248 C 0x249): trig2_cfg_1 .................................. 230 0x258 C 0x25f: reserved ............................................................................................................................................... 230 trigger output unit 3 target time and output configuration/control registers (0x260 C 0x277) ................................ . 230 0x278 C 0x27f: reserved ............................................................................................................................................... 230 trigger output unit 4 target time and output configuration/control registers (0x280 C 0x297) ................................ . 230 0x298 C 0x29f: reserved ............................................................................................................................................... 230 trig ger output unit 5 target time and output configuration/control registers (0x2a0 C 0x2b7) ................................ 230 0x2b8 C 0x2bf: reserved ............................................................................................................................................... 230 trigger output unit 6 target time and output configuration/control registers (0x2c0 C 0x2d7) ................................ 230 0x2d8 C 0x2df: reserved .............................................................................................................................................. 230 trig ger output unit 7 target time and output configuration/control registers (0x2e0 C 0x2f7) ................................ 231 0x2f8 C 0x2ff: reserved ............................................................................................................................................... 231 trigger output unit 8 target time and output configuration/control registers (0x300 C 0x317) ................................ . 231 0x318 C 0x31f: reserved ............................................................................................................................................... 231 trig ger output unit 9 target time and output configuration/control registers (0x320 C 0x337) ................................ . 231 0x338 C 0x33f: reserved ............................................................................................................................................... 231 trigger output unit 10 target time and output configuration/control registers (0x340 C 0x357) ............................... 231 0x358 C 0x35f: reserved ............................................................................................................................................... 231 trigger output unit 11 target time and output configuration/control registers (0x360 C 0x377) ............................... 231 0x378 C 0x37f: reserved ............................................................................................................................................... 231 trigger output unit 12 target time and output configuration/control registers (0x380 C 0x397) ............................... 231 0x398 C 0x3ff: reserved ............................................................................................................................................... 231 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 14 revision 1.0 internal i/o register space mapping for ptp timestamp inputs (12 units, 0x400 C 0x5ff) ............................................ 232 timestamp ready register (0x400 C 0x401): ts_rdy ................................................................................................ . 232 timestamp enable register (0x402 C 0x403): ts_en ................................................................................................... 232 timestamp software reset register (0x404 C 0x405): ts_sw_rst ............................................................................ 232 0x406 C 0x41f: reserved ............................................................................................................................................... 232 ti mestamp unit 1 status register (0x420 C 0x421): ts1_status ............................................................................... 233 timestamp unit 1 configuration and control register (0x422 C 0x423 ): ts1_cfg ...................................................... 233 timestamp unit 1 input 1st sample time in nanoseconds low?word register (0x424 C 0x425): ts1_smpl1_nsl ........................................................................................................................................................ 234 timestamp unit 1 input 1st sample time in nanoseconds high?word register (0 x426 C 0x427): ts1_smpl1_nsh ........................................................................................................................................................ 234 timestamp unit 1 input 1st sample time in seconds low?word register (0x428 C 0x429): ts1_smpl1_sl ........................................................................................................................................................... 234 timestamp unit 1 input 1st sample time in seconds high?word register (0x42a C 0x42b): ts1_smpl1_sh .......................................................................................................................................................... 234 timestamp unit 1 input 1st sample time in sub?nanoseconds register (0x42c C 0x42d): ts1_smpl1_sub_ns ................................................................................................................................................. 235 0x42e C 0x433: reserved ............................................................................................................................................... 235 time stamp unit 1 input 2nd sample time in nanoseconds low?word register (0x434 C 0x435): ts1_smpl2_nsl ........................................................................................................................................................ 235 timestamp unit 1 input 2nd sample time in nanoseconds high?word register (0x436 C 0x437): ts1_smpl2_nsh ........................................................................................................................................................ 235 timestamp unit 1 input 2nd sample time in seconds low?word register (0x438 C 0x439): ts1_smpl2_sl ........................................................................................................................................................... 235 timestamp unit 1 input 2nd sample time in seconds high?word register (0x43a C 0x43b): ts1_smpl2_sh .......................................................................................................................................................... 236 timestamp unit 1 input 2nd sample time in sub?nanoseconds register (0x43c C 0x43d): ts1_smpl2_sub_ns ................................................................................................................................................. 236 0x43e C 0x43f: reserved ............................................................................................................................................... 236 timestamp unit 2 status/configuration/control and input 1st sample time registers (0x 440 C 0x44d) ...................... 236 0x44e C 0x453: reserved ............................................................................................................................................... 236 timestamp unit 2 input 2nd sample time registers (0x454 C 0x45d) .......................................................................... 236 0x45e C 0x45f: reserved ............................................................................................................................................... 236 timestamp unit 3 status/configuration/control and input 1st sample time registers (0x 460 C 0x46d) ...................... 236 0x46e C 0x473: reserved ............................................................................................................................................... 236 timestamp unit 3 input 2nd sample time registers (0x474 C 0x47d) .......................................................................... 237 0x47e C 0x47f: reserved ............................................................................................................................................... 237 timestamp unit 4 status/configuration/control and input 1st sample time registers (0x 480 C 0x48d) ...................... 237 0x48e C 0x493: reserved ............................................................................................................................................... 237 time stamp unit 4 input 2nd sample time registers (0x494 C 0x49d) .......................................................................... 237 0x49e C 0x49f: reserved ............................................................................................................................................... 237 timestamp unit 5 status/configuration/control and input 1st sample time registers (0x 4a0 C 0x4ad) ..................... 237 0x4ae C 0x4b3: reserved .............................................................................................................................................. 237 timestamp unit 5 input 2nd sample time registers (0x4b4 C 0x4bd) ......................................................................... 237 0x4be C 0x4bf: reserved .............................................................................................................................................. 237 timestamp unit 6 status/configuration/control and input 1st sample time registers (0x 4c0 C 0x4cd) .................... 237 0x4ce C 0x4d3: reserved .............................................................................................................................................. 237 timestamp unit 6 input 2nd sample time registers (0x4d4 C 0x4dd) ......................................................................... 238 0x4de C 0x4df: reserved .............................................................................................................................................. 238 timestamp unit 7 status/configuration/control and input 1st sample time registers (0x 4e0 C 0x4ed) ..................... 238 0x4ee C 0x4f3: reserved ............................................................................................................................................... 23 8 timestamp unit 7 input 2nd sample time registers (0x4f4 C 0x4fd) .......................................................................... 238 0x4fe C 0x4ff: reserved ............................................................................................................................................... 238 timestamp unit 8 status/configuration/control and input 1st sample time registers (0x 500 C 0x50d) ...................... 238 0x50e C 0x513: reserved ............................................................................................................................................... 238 timestamp unit 8 input 2nd sample time registers (0x514 C 0x51d) .......................................................................... 238 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 15 revision 1.0 0x51e C 0x51f: reserved ............................................................................................................................................... 238 time stamp unit 9 status/configuration/control and input 1st sample time registers (0x520 C 0x52d) ...................... 238 0x52e C 0x533: reserved ............................................................................................................................................... 238 timestamp unit 9 input 2nd sample time registers (0x534 C 0x53d) .......................................................................... 239 0x53e C 0x53f: reserved ............................................................................................................................................... 239 time stamp unit 10 status/configuration/control and input 1st sample time registers (0x540 C 0x54d) .................... 239 0x54e C 0x553: reserved ............................................................................................................................................... 239 timestamp unit 10 input 2nd sample time registers (0x554 C 0x55d) ........................................................................ 239 0x55e C 0x55f: reserved ............................................................................................................................................... 239 timestamp unit 11 status/configuration/control and input 1st sample time registers (0x560 C 0x56d) .................... 239 0x56e C 0x573: reserved ............................................................................................................................................... 239 timestamp unit 11 input 2nd sample time registers (0x574 C 0x57d) ........................................................................ 239 0x57e C 0x57f: reserved ............................................................................................................................................... 239 timestamp unit 12 status/configuration/control and input 1st sample time registers (0x580 C 0x58d) .................... 239 0x58e C 0x593: reserved ............................................................................................................................................... 239 timestamp unit 12 input 2nd sample time registers (0x594 C 0x59d) ........................................................................ 240 0x59e C 0x5a3: reserved ............................................................................................................................................... 240 timestamp unit 12 input 3rd sample time registers (0x5a4 C 0x5ad) ........................................................................ 240 0x5ae C 0x5b3: reserved .............................................................................................................................................. 240 time stamp unit 12 input 4th sample time registers (0x5b4 C 0x5bd) ........................................................................ 240 0x5be C 0x5c3: reserved .............................................................................................................................................. 240 timestamp unit 12 input 5th sample time registers (0x5c4 C 0x5cd) ........................................................................ 240 0x5ce C 0x5d3: reserved .............................................................................................................................................. 240 time stamp unit 12 input 6th sample time registers (0x5d4 C 0x5dd) ........................................................................ 240 0x5de C 0x5e3: reserved .............................................................................................................................................. 240 timestamp unit 12 input 7th sample time registers (0x5e4 C 0x5ed) ........................................................................ 240 0x5ee C 0x5f3: reserved ............................................................................................................................................... 240 timestamp unit 12 input 8th sample time registers (0x5f4 C 0x5fd) ......................................................................... 241 0x5fe C 0x5ff: reserved ............................................................................................................................................... 241 internal i/o register space mapping for ptp 1588 clock and global control (0x600 C 0x7ff) ....................................... 242 ptp clock control register (0x600 C 0x601): ptp_clk_ctl ...................................................................................... 242 0x602 C 0x603: reserved ................................................................................................................................................ 242 ptp real time clock in nanoseconds low?word register (0x604 C 0x605): ptp_rtc_nsl .................................... 243 ptp real time clock in nanoseconds high?word register (0x606 C 0x607): ptp_rtc_nsh .................................. 243 ptp real time clock in seconds low?word register (0x608 C 0x609): ptp_rtc_sl .............................................. 243 ptp real time clock in seconds high?word register (0x60a C 0x60b): ptp_rtc_sh ............................................ 243 ptp real time clock in phase register (0x60c C 0x60d): ptp_rtc_phase ........................................................... 244 0x60e C 0x60f: reserved ............................................................................................................................................... 244 ptp rate in sub?nanoseconds low?word register (0x610 C 0x611): ptp_sns_rate_l ....................................... 244 ptp rate in sub?nanoseconds high?word and control register (0x612 C 0x613): ptp_sns_rate_h ..................................................................................................................................................... 245 ptp temporary adjustment mo de duration in low?word register (0x614 C 0x615): ptp_temp_adj_dura_l .......................................................................................................................................... 245 ptp temporary adjustment mode duration in high?word register (0x616 C 0x617): ptp_temp_adj_dura_h ......................................................................................................................................... 245 0x618 C 0x61f: reserved ............................................................................................................................................... 245 ptp message configuration 1 register (0x620 C 0x621): ptp_msg_cfg_1 .............................................................. 246 ptp message configuration 2 register (0x622 C 0x623): ptp_msg_ cfg_2 .............................................................. 247 ptp domain and version register (0x624 C 0x625): ptp_domain_ver ................................................................... 248 0x626 C 0x63f: reserved ............................................................................................................................................... 248 ptp port 1 receive latency register (0x640 C 0x641): ptp_p1_rx_latency ........................................................ 248 ptp port 1 transmit latency register (0x642 C 0x643): ptp_ p1_tx_latency ........................................................ 249 ptp port 1 asymmetry correction register (0x644 C 0x645): ptp_p1_asym_cor ................................................... 249 ptp port 1 link delay register (0x646 C 0x647): ptp_p1_link_dly ......................................................................... 249 ptp port 1 egress timestamp low?word register for pdelay_req and delay_re q (0x648 C 0x649): p1_xdly_req_tsl ................................................................................................................................................... 249 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 16 revision 1.0 ptp port 1 egress timestamp high?word register for pdelay_req and delay_req (0x64a C 0x64b): p1_xdly_req_tsh ................................................................................................................................................... 250 ptp port 1 egress timestamp low?word register for sync (0x64c C 0x64d): p1_sync_tsl ................................ . 250 ptp port 1 egress timestamp high?word register for sync (0x64e C 0x64f): p1_sync_tsh ................................ 250 ptp port 1 egress timestamp low?word register for pdelay_resp (0x650 C 0x651): p1_pdly_resp_tsl .......... 250 ptp port 1 egress timestamp high?word register for pdelay_resp (0x652 C 0x653): p1_pdly_resp_tsh ........ 250 0x654 C 0x65f: reserved ............................................................................................................................................... 251 ptp port 2 receive latency register (0x660 C 0x661): ptp_p2_rx_latency ........................................................ 251 ptp port 2 transmit latency register (0x662 C 0x663): ptp_p2_tx_latency ........................................................ 251 ptp port 2 asymmetry correction register (0x664 C 0x665): ptp_p2_asym_cor ................................................... 251 ptp port 2 link delay register (0x666 C 0x667): ptp_p2_link_dly ......................................................................... 251 ptp port 2 egress timestamp low?word register for pdelay_req and delay _req (0x668 C 0x669): p2_xdly_req_tsl ................................................................................................................................................... 251 ptp port 2 egress timestamp high?word register for pdelay_req and delay_req (0x66a C 0x66b): p2_xdly_req_tsh ................................................................................................................................................... 252 ptp port 2 egress timestamp low?word register for sync (0x66c C 0x66d): p2_sync_tsl ................................ . 252 ptp port 2 egress timestamp high?word register for sync (0x66e C 0x66f): p2_sync_tsh ................................ 252 ptp port 2 egress timestamp low?word register for pdelay_resp (0x670 C 0x671): p2_pdly_resp_tsl .......... 252 ptp port 2 egress timestamp high?word register for pdelay_resp (0x672 C 0x673): p2_pdly_resp_tsh ........ 252 0x674 C 0x67f: reserved ............................................................................................................................................... 253 gpio monitor register (0x680 C 0 x681): gpio_monitor ........................................................................................... 253 gpio output enable register (0x682 C 0x683): gpio_oen ......................................................................................... 253 0x684 C 0x687: reserved ................................................................................................................................................ 253 ptp trigger unit interrupt status register (0x688 C 0x689): ptp_trig_is ................................................................ . 253 ptp trigger unit interrupt enable register (0x68a C 0x68b): ptp_trig_ie ............................................................... 253 ptp timest amp unit interrupt status register (0x68c C 0x68d): ptp_ts_is .............................................................. 254 ptp timestamp unit interrupt enable register (0x68e C 0x68f): ptp_ts_ie ............................................................. 254 0x690 C 0x733: reserved ................................................................................................................................................ 255 dsp control 1 register (0x734 C 0x735): dsp_cntrl_6 ............................................................................................ 255 0x736 C 0x747: reserved ................................................................................................................................................ 255 analog control 1 register (0x748 C 0x749): ana_cntrl_1 ......................................................................................... 255 analog control 3 register (0x74c C 0x74d): ana_cntrl_3 ....................................................................................... 256 0x74e C 0x7ff: reserved ............................................................................................................................................... 256 mana gement information base (mib) counters ................................................................................................................. 257 mib counter examples: ................................................................................................................................................... 259 additional mib information .............................................................................................................................................. 259 static mac address table .................................................................................................................................................. 260 st atic mac table lookup examples: .............................................................................................................................. 261 dynamic mac address table ............................................................................................................................................. 262 dynamic mac address lookup example: ...................................................................................................................... 262 vlan table ......................................................................................................................................................................... 263 vlan table looku p examples: ....................................................................................................................................... 263 absolute maximum ratings ................................................................................................................................................ 264 operating ratings ............................................................................................................................................................... 264 electrical characteristics ..................................................................................................................................................... 264 timing specifications .......................................................................................................................................................... 268 host interface read / write timing ................................................................................................................................ . 268 auto?negotiation timing ................................................................................................................................................. 269 trigger output unit and timestamp input unit timing .................................................................................................... 270 serial eeprom interface timing .................................................................................................................................... 272 reset timing and power sequencing ................................................................................................................................ . 273 reset circuit guidelines ...................................................................................................................................................... 274 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 17 revision 1.0 reference circuits C led strap - in pins .............................................................................................................................. 275 reference clock C connection and selection .................................................................................................................... 276 selection of reference crystal ............................................................................................................................................ 276 selection of isolation transformers ..................................................................................................................................... 277 package information and recommended landing pattern ................................................................................................ 278 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 18 revision 1.0 list of figures figure 1. typical straight cable connection ........................................................................................................................ 33 figure 2. typical crossover cable connection .................................................................................................................... 33 figure 3. auto negotiation and parallel operation ............................................................................................................... 34 figure 4. near - end and far - end loopback .......................................................................................................................... 36 figure 5. destination address lookup flow chart in stage one ......................................................................................... 38 figure 6. destination address resolution flow chart in stage two .................................................................................... 39 figure 7. tail tag frame format .......................................................................................................................................... 44 figure 8. 802.1p priority field format .................................................................................................................................. 48 figure 9. host tx single frame in manual enqueue flow diagram .................................................................................... 52 figure 10. host rx single or multiple frames in auto - dequeue flow diagram .................................................................. 55 figure 11. ptp system clock overview ............................................................................................................................... 58 figure 12. trigger output unit organization and associated registers ............................................................................... 65 figure 13. timestamp input unit organization and associated registers ........................................................................... 66 figure 14. trigger unit interrupts .......................................................................................................................................... 67 figure 15. timestamp input unit interrupts .......................................................................................................................... 67 figure 16. complex waveform generation using cascade mode ....................................................................................... 71 figure 17. recommended low - voltage power connection using an external low - voltage - regulator .............................. 75 figu re 18. recommended low - voltage power connections using the internal low - voltage regulator ............................ 76 figure 19. traffic activity and eee ....................................................................................................................................... 78 figure 20. ksz8462 8 - bit and 16 - bit data bus connections ............................................................................................... 84 figure 21. interface and register mapping ........................................................................................................................... 86 figure 22. host interfac e read/write timing ...................................................................................................................... 268 figure 23. auto - negotiation timing .................................................................................................................................... 269 figure 24. trigger output unit and timestamp input unit timing ...................................................................................... 270 figure 25. serial eeprom timing ..................................................................................................................................... 272 figure 26. ksz8462 reset and power sequence timing .................................................................................................. 273 figure 27. sample reset circuit ......................................................................................................................................... 274 figure 28. recommended reset circuit for interfacing with a cpu/fpga reset output ................................................. 274 figure 29. typical led strap - in circuit .............................................................................................................................. 275 figure 30. 25mhz crystal and oscillator clock connection options ................................................................................. 276 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 19 revision 1.0 list of tables table 1. mdi/mdi - x pin definitions ...................................................................................................................................... 32 table 2. mac address filtering scheme .............................................................................................................................. 42 table 3. spanning tree states ............................................................................................................................................. 43 table 4. tail tag rules ......................................................................................................................................................... 45 tabl e 5. fid + da lookup in vlan mode ............................................................................................................................ 46 table 6. fid + sa lookup in vlan mode ............................................................................................................................ 47 table 7. frame format for transmit queue ......................................................................................................................... 50 table 8. transmit control word bit fields ............................................................................................................................ 50 table 9. transmit byte count format ................................................................................................................................... 51 table 10. register setting for transmit function block ....................................................................................................... 51 table 11. frame format for receive queue ........................................................................................................................ 53 table 12. register settings for receive function block ....................................................................................................... 54 table 13. ksz8462 gpio pin resources ............................................................................................................................. 63 table 14. trigger output units and timestamp input units summary ................................................................................. 64 table 15. gpio pin control register layout ........................................................................................................................ 64 table 16. ksz8462 device clocks ....................................................................................................................................... 74 table 17. voltage options and requirements ...................................................................................................................... 75 table 18. power management and internal blocks .............................................................................................................. 77 table 19. available interfaces ............................................................................................................................................... 82 table 20. bus interface unit signal grouping ....................................................................................................................... 83 table 21. ksz8462 serial eeprom format ........................................................................................................................ 85 table 22. mapping of functional areas within the address space ...................................................................................... 87 table 23. ingress or egress data rate limits .................................................................................................................... 154 table 24. format of per - port mib counters ....................................................................................................................... 257 table 25. port 1 mib counters ? indirect memory offset ................................................................................................... 258 table 26. "all ports dropped packet" mib counter format ............................................................................................... 259 table 27. "all ports dropped packet" mib counters? indirect memory offsets ................................................................ . 259 table 28. static mac table format (8 entries) .................................................................................................................. 260 table 29. dynamic mac address table format (1024 entries) ......................................................................................... 262 table 30. vlan table format (16 entries) ......................................................................................................................... 263 table 31. host interface read/write timing parameters ................................................................................................... 268 table 32. auto - negotiation timing parameters .................................................................................................................. 269 table 33. trigger output unit and timestamp input unit timing parameters ................................................................... 271 table 34. serial eeprom timing parameters ................................................................................................................... 272 table 35. reset timing parameters ................................................................................................................................... 273 table 36. typical reference crystal characteristics .......................................................................................................... 276 table 37. transformer selection criteria ............................................................................................................................ 277 table 38. qualified single port magnetic ............................................................................................................................ 277 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 20 revision 1.0 acronyms biu bus interface u nit the host interface function that performs code conversion , buffering, and the like required for communications to and from a network . bpdu bridge protocol data unit a packet containing ports, addresses, etc. to make sure data being passed through a bridged network arrives at its proper destination. cmos complementary metal oxide semiconductor a common semiconductor manufacturing technique in which positive and negative types of transistors ar e combined to form a current gate that in turn forms an effective means of controlling electrical current through a chip. crc cyclic redundancy check a common technique for detecting data transmiss ion errors. crc for ethernet is 32 bits long. cut - through switch a switch typically processes received packets by reading in the full packet (storing), then processing the packet to determine where it needs to go, then forwarding it. a cut?through switch simply reads in the first bit of an incoming packet and forwards the packet. cut?through switches do not store the packet. da destination address the address to send packets. dma direct memory access a design in which memory on a chip is controlled independently of the cpu. emi electromagnetic interference a naturally occurring phenomena when the electromagnetic field of one device disrupts, impedes or degrades the electromagnetic field of another device by coming into proximity with it. in computer tec hnology, computer devices are susceptible to emi because electromagnetic fields are a byproduct of passing electricity through a wire. data lines that have not been properly shielded are susceptible to data corruption by emi. fcs frame check sequence see crc. fid frame or filter id specifies the frame identifier. alternately is the filter identifier. gpio general purpose input/output general purpose input/output pins are signal pins that can be controlled or monitored by hardware and software to perform specific tasks. igmp internet group management protocol the protocol defined by rfc 1112 for ip multicast transmissions. ipg inter - packet gap a time delay between successive data packets mandated by the network standard for protocol reasons. in ethernet, the medium has to be "silent" (i.e., no data transfer) for a short period of time before a node can consider the network idle and start to transmit. ipg is used to correct timing differences between a transmitter and receiver. during the ipg, no data is transferred, and information in the gap can be discarded or additions inserted without impact on data integrity. isi inter - symbol interference the disruption of transmitted code caused by adjacent pulses affecting or interfering with each other. isa industry standard architecture a bus architecture used in the ibm pc/xt and pc/at. jumbo packet a packet larger than the standard ethernet packet (1500 bytes). large packet sizes allow for more efficient use of bandwidth, lower overhead, less processing, etc. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 21 revision 1.0 acronyms (continued) mac media access controller a functional block responsible for implementing the media access control layer which is a sub layer of the data link layer . mdi medium dependent interface an ethernet port connection that allows network hubs or switches to connect to other hubs or switches without a null?modem, or crossover, cable. mdi provides the standard interface to a particular media (copper or fiber) and is therefor e media dependent. mdi -x medium dependent interface crossover an ethernet port connection that allows networked end stations (i.e., pcs or workstations) to connect to each other using a null?modem, or crossover, cable. for 10/100 full?duplex networks, an end point (such as a computer) and a switch are wired so that each transmitter connects to the far end receiver. when connecting two computers together, a cable that crosses the tx and rx is required to do this. with auto mdi?x, the phy senses the corre ct tx and rx roles, eliminating any cable confusion. mib management information base the mib comprises the management portion of network devices. this can include things like monitoring traffic levels and faults (statistical), and can also change operating parameters in network nodes (static forwarding addresses). mii media independent interface the mii accesses phy registers as defined in the ieee 802.3 specification. nic network interface card an expansion board inserted into a computer to allow it to be connected to a network. most nics are designed for a particular type of network, protocol, and media, although some can serve multiple networks. npvid non - port vlan id the port vlan id value is used as a vlan reference. nrz non - return to zero a type of signal data encoding whereby the signal does not return to a zero state in between bits. phy a device or functional block which performs the physical layer interface function in a network. pll phase - locked loop an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference, signal. a pll ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate, and demodulate a signal and divide a frequency. ptp precision time protocol a protocol, ieee 1588 as applied to this device, for synchronizing the clocks of devices attached to a specific network. qmu queue management unit manages packet traffic between the port 3 internal mac and the system host (processor) interface . the qmu has built?in packet memories for receive and transmit functions called txq (transmit queue) and rxq (receive queue). for the qmu, transmit means into port 3 of the switch from the external host, and receive is from the switch to the external host. this terminology is the opposite of the terminology used for other ksz8462 switch blocks. sa source address the address from which information has been sent. tsu timestamp input unit the functional block which captures signals on the gpio pins and assigns a time to the specific event. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 22 revision 1.0 acronyms (continued) tdr time domain reflectometry tdr is used to pinpoint flaws and problems in underground and aerial wire, cabling, and fiber optics. they send a signal down the conductor and measure the time it takes for the whole or part of the signal to return. tsu timestamp input unit the functional block which captures signals on the gpio pins and assigns a time to the specific event. utp unshielded twisted pair commonly a cable containing 4 twisted pairs of wires. the wires are twisted in such a manner as to cancel electrical interference generated in each wire, therefore shielding is not required. vlan virtual local area network a confi guration of computers that acts as if all computers are connected by the same physical network but which may be located virtually anywhere. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 23 revision 1.0 pin configuration 64 - pin lqfp downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 24 revision 1.0 pin description pin number pin name type pin function 1 rxm1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (? differential ). 2 rxp1 i/o port 1 physical receive (mdi) or transmit (mdix) signal (+ differential). 3 agnd gnd analog ground. 4 txm1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (? differential). 5 txp1 i/o port 1 physical transmit (mdi) or receive (mdix) signal (+ differential). 6 vdd_al p this pin is used as an input for the low - voltage analog power. its source should have appropriate filtering with a ferrite bead and capacitors. 7 iset o current set : sets the physical transmit output current. pull?down this pin with a 6.49k (1%) resistor to ground. 8 agnd gnd analog ground. 9 vdd_a3.3 p 3.3v analog vdd input power supply (must be well decoupled). 10 rxm2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (? differential). 11 rxp2 i/o port 2 physical receive (mdi) or transmit (mdix) signal (+ differential). 12 agnd gnd analog ground. 13 txm2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (? differential). 14 txp2 i/o port 2 physical transmit (mdi) or receive (mdix) signal (+ differential). 15 fxsd2 i fiber signal detect input for port 2 in 100 base ? fx fiber mode. when in copper mode, this input is unused and should be pulled to gnd. note: this functionality is available only on the ksz8462fhl. 16 vdd_col p this pin is used as a second input for the low - voltage analog power. its source should have appropriate filtering with a ferrite bead and capacitors. 17 pwrdn ipu full?chip power?down : active low (low = p ower down; high or floating = n ormal operation). while this pin is asserted low, a ll i/o pins will be tri ? state d. all registers will be set to their default state. while this pin is asserted, power consumption will be minimal. when the pin is de?asserted, power consumption will climb t o nominal and the device will be in the same state as having been reset by the reset pin (rstn, pin 63). 18 x1 i 25 mhz c rystal or os cillator c lock c onnection : pins (x1, x2) connect to a crystal or frequency oscillator source. if an oscillator is used, x1 connects to a vdd_io voltage tolerant oscillator and x2 is a no connect. this clock requirement is 50ppm. 19 x2 o legend: p = power supply gnd = ground i/o = bi?directional i = input o = output. ipd = input with internal pull?down (58k 30%). ipu = input with internal pull?up (58k 30%). opd = output with internal pull?down (58k 30%). opu = output with internal pull?up (58k 30%). ipu/o = input with internal pull?up (58k 30%) during power?up/reset; output pi n otherwise. ipd/o = input with internal pull?down (58k 30%) during power?up/reset; output pin otherwise. i/o (pd) = bi?directional input/output with intern al pull?down (58k 30%). i/o (pu) = bi?directional input/output with internal pull?up (58k 30%). downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 25 revision 1.0 pin description (continued) pin number pin name type pin function 20 dgnd gnd digital ground 21 vdd_io p 3.3v, 2.5v or 1.8v digital vdd input power pin for io logic and the internal low - voltage regulator. 22 sd15/be3 i/o (pd) shared data bus bit[15] or be3: this is data bit (d15) access when cmd = 0. this is byte enable 3 (be3, 4th byte enable and active high) at double?wor d boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gn d in 8?bit bus mode. 23 sd14/be2 i/o (pd) shared data bus bit [ 14] or be2: this is data bit (d14) access when cmd = 0. this is byte enable 2 (be2, 3rd byte enable and active high) at double?word boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gn d in 8?bit bus mode. 24 sd13/be1 i/o (pd) shared data bus bit [ 13] or be1: this is data bit (d13) access when cmd = 0. this is byte enable 1 (be1, 2nd byte enable and active high) at double?word boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gn d in 8?bit bus mode. 25 sd12/be0 i/o (pd) shared data bus bit [ 12] or be0 : this is data bit (d12) access when cmd = 0. this is byte enab le 0 (be0, 1st byte enable and active high) at double?word boundary access in 16?bit bus mode when cmd = 1. this pin must be tied to gn d in 8?bit bus mode. 26 sd11 i/o (pd) shared data bus bit [ 11] : this is data bit (d11) access when cmd = 0. dont care when cmd = 1. this pin must be tied to gnd in 8?bit bus mode. 27 sd10/a10 i/o (pd) shared data bus bit [ 10] : this is data bit (d10) access when cmd = 0. in 8?bit bus mode, this pin must be tied to gnd. in 16?bit bus mode, this is address a 10 acces s when cmd = 1. 28 sd9/a9 i/o (pd) shared data bus bit[ 9] or a9 : this is data bit (d9) access when cmd = 0. in 8?bit bus mode, this pin must be tied to gnd. in 16?bit bus mode, this is ad dress a9 access when cmd = 1. 29 dgnd gnd digital ground . 30 vdd_io p 3.3v, 2.5v or 1.8v digital vdd input power pin for io logic and the internal low - voltage regulator . 31 sd8/a8 ipu/o shared data bus bit [ 8] or a8 : this is data bit (d8) access when cmd = 0. in 8?bit bus mode, this pin must be tied to gnd. in 16?bit bus mode, this is address a8 access when cmd = 1. 32 sd7/a7 ipd/o shared data bus bit [ 7] or a7 : this is data bit (d7) access when cmd = 0. in 8?bit bus mode, this is address a7 (1 st write) or dont care (2 nd write) access when cmd = 1. in 16?bit bus mode, this is address a7 access when cmd = 1. 33 sd6/a6 ipu/o shared data bus b it [ 6] or a6: this is data bit (d6) access when cmd = 0. in 8?bit bus mode, this is address a6 (1 st write) or dont care (2 nd wr ite) access when cmd = 1. in 16?bit bus mode, this is address a6 access when cmd = 1. 34 sd5/a5 ipu/o shared data bus bit [ 5] or a5 : this is data bit (d5) access when cmd = 0. in 8?bit bus mode, this is address a5 (1 st write) or dont care (2 nd write) access when cmd = 1. in 16?bit bus mode, this is address a5 access when cmd = 1. 35 sd4/a4 ipd/o shared data bus bit [ 4] or a4 : this is data bit (d4) access when cmd = 0. in 8?bit bus mode, this is address a4 (1 st write) or dont care (2 nd wr ite) access when cmd = 1. in 16?bit bus mode, this is address a4 access when cmd = 1. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 26 revision 1.0 pin description (continued) pin number pin name type pin function 36 sd3/a3 i/o (pd) shared data bus bit [ 3] or a3 : this is data bit (d3) access when cmd = 0. in 8?bit bus mode, this is address a3 (1 st write) or dont care (2 nd write) access when cmd = 1. in 16?bit bus mode, this is address a3 access when cmd = 1. 37 sd2/a2 i/o (pd) shared data bus bit [ 2] or a2 : this is data bit (d2) access when cmd = 0. in 8?bit bus mode, this is address a2 (1 st write) or a10 (2 nd write) access when cmd = 1. in 16?bit bus mode, this is address a2 access when cmd = 1. 38 sd1/a1/a9 i/o (pd) shared data bus bit [ 1] or a1 or a9 : this is data bit (d1) access when cmd = 0. in 8?bit bus mode, this is address a1 (1 st write) or a9 (2 nd write) access when cmd = 1. in 16?bit bus mode, this is dont care when cmd = 1. 39 dgnd gnd digital ground. 40 vdd_l p this pin can be used in two ways; as the pin to input the low volta ge to the device if the internal low - voltage regulator is not used, or as the low - voltage output if the internal low - voltage regulator is used. 41 sd0/a0/a8 ipu/o shared data bus bit [ 0] or a0 or a8 : this is data bit (d0) access when cmd = 0. in 8?bit bus mode, this is address a0 (1 st write) or a8 (2 nd write) access when cmd = 1. in 16?bit bus mode, this is dont care when cmd = 1. 42 cmd ipd command type : this command input decides the sd[15:0] shared data bus access information. when command in put is low, the access of shared data bus is for data access either sd[15:0] ?> data[15:0] in 16?bit bus mode or sd[7:0] ?> data[7:0] in 8?bit bus mode. when command input is high, in 16?bit bus mode: the access of shared data bu s is for address a[10:2] access at shared data bus sd[10:2] and sd[1:0] is dont care". byte enable be[3:0] at sd[15:12] and the sd[11] is dont care. in 8?bit b us mode: it is for address a[7:0] during 1 st write access at shared data bus sd[7:0] or a[10:8] during 2 nd write access at shared data bus sd[2:0] (sd[7:3] is dont care). 43 intrn opu interrupt output : this is an active low signal going to the host cpu to indicate an interrupt status bit is set. this pin needs an external 4.7k pull?up resistor. 44 rdn ipu read strobe : this signal is an active low signal used as the a synchronous read strobe during read acces s cycles by the host processor. it is recommended that it be pulled up with a 4.7k C ohm resistor. 45 wrn ipu write strobe: this is an a synchronous write strobe signal used during write cycles from the external host processor. it is a low active signal. 46 pme/eeprom ipd/o power management event: this output signal indicates that a wake - on - lan event has been detected. the ksz8462 is requesting the system to wake up from low power mode. its assertion polarity is programmable with the default polarity to be active low. config mode: (eeprom) : at the end of the power up / reset period, this pin is sampled and the pull ? up/pull ? down value is latched. the value latched will indicate if a s erial eeprom is present or not. see the strapping options section for detail s. 47 csn ipu chip select: this signal is the chip - select signal that is used by the ex ternal host processor for accesses to the device. it is an active low si gnal. 48 gpio0 i/o(pu) general purpose input/output [0] : this pin can be used as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 clock. the h ost p rocessor can also directly drive or read this gpio pin. 49 gpio1 i/o(pu) general purpose input/output [1] : re fer to gpio0 pin 48 description . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 27 revision 1.0 pin description (continued) pin number pin name type pin function 50 dgnd gnd digital ground. 51 vdd_l p this pin can be used in two ways; as the pin to input the low voltage to the device if the internal low - voltage regulator is not used, or as the low - voltage output if the internal low - voltage regulator is used. 52 gpio2 i/o(pu) this pin is gpio2 (refer to gpio0 pin 48 description). 53 gpio3/eesk i/o(pd) default function: eeprom serial clock output : a serial output clock is used to load configuration data into the ksz8462 from the external eeprom when it is present. alternate function: general purpose input/output [3]: this pin can be used as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 clock. the host processor can also directly drive or read this gpio pin. function of this pin is controlled by bit[5] in iomxsel register. 54 gpio4/eedio i/o(pd) default function: eeprom data input/output: serial data input/output is from/to external eeprom when it is present. alternate function: general purpose input/output [4] : this pin can be used as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 clock. the host p rocessor can also directly drive or read this gpio pin. function of this pin is con trolled by b it[2] in iomxsel register. 55 gpio5/eecs i/o(pd) default function: eeprom chip select output: this signal is used to select an external eeprom device when it is present. alternate function: general purpose input/output [5] : this pin can be us ed as an input or output pin for use by the ieee 1588 event trigger or timestamp capture units. it will be synchronized to the internal ieee 1588 clock. the host p rocessor can also directly drive or read this gpio pin. function of this pin is controlled by bit[1] in iomxsel register. 56 vdd_io p 3.3v, 2.5v or 1.8v digital vdd input power pin for io logic and the internal low - v oltage regulator . 57 dgnd gnd digital ground . 58 gpio6 i/o(pu) general purpose input/output [6] : r e fer to gpio0 pin 48 description . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 28 revision 1.0 pin description (continued) pin number pin name type pin function 59 p1led1 ipu /o programmable led outputs to indicate port 1 and port 2 activity/s tatus: the led is on (active) when output is low; the led is off (inactive) when output is high. the port 1 led pins outputs are determined by the table below if reg. 0x06c C 0x06d, bits [ 14:12] are set to 000. otherwise, the port 1 led pins are controlled via the processor by setting reg. 0x06c C 0x06d, bits[ 14:12] to a non - zero value. the port 2 led pins outputs are determined by the table below if reg. 0x084 C 0x085, bits[ 14:12] are set to 000. otherwise, the port 2 led pins are controlled via the processor by setting reg. 0x084 C 0x085, bits[ 14:12] to a non - zero value. automatic port 1 and port 2 indicators are defined as follows: two bits[ 9:8] in sgcr7 control register 00 (default) 01 10 11 p1led1/p2led1 speed act duplex duplex p1led0/p2led0 link/act link link/act link link = led on act = led blink link/act = led on/blink speed = led on (100bt) led off (10bt) duplex = led on (full duplex) led off (half duplex) config mode: (p1led1): at the end of the power up / reset period, this pin is sampled and the pull - up/pull - down value is latched. it must be at a logic high level at this time. see the strapping options section for details. config mode: (p1led0/h816) : at the end of the power up / reset period, this pin is sampled and the pull?up/pull?down value is latched. the value latched will determine if 8?bit or 16?bit mode will be used for the host interface. see the strapping options section for details. config mode: (p2led0/lebe) : at the end of the power up / reset period, this pin is sampled and the pull?up/pull?down value is latched. the value latched will determine if little endian or big endian mode will be used for the host interface. see the strapping options section for details. 60 p1led0/h816 ipu /o 61 p2led1 o 62 p2led0/lebe ipu /o 63 rstn ipu reset : hardware reset pin. (active low) this reset input is required to be low for a minimum of 10 ms after supply voltages vdd_io and 3.3v are stable. 64 fxsd1 i fiber signal detect : fiber signal detect input for port 1 in 100 base ? fx fiber mode. when in copper mode, this input is unused and should be pulled to gnd. note : this functionality is available only on the ksz8462fhl device. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 29 revision 1.0 strapping options pin number pin name type pin function during power - up / reset 46 pme/ eeprom ipd /o eeprom select pull?up = eeprom present , nc or p ull? down (default ) = eeprom not present. this pin value is latched into register ccr, bit [9] at the end of the power - on - reset time. 59 p1led1 ipu/o reserved nc or pull - up (default) = normal operation , pull- down = reserved 60 p1led0/ h816 ipu/o 8 or 16?bit bus mode select nc or p ull? up (default ) = 16?bit bus mode , p ull?down = 8?bit bus mode . this pin value is also latched int o register ccr, bit [7:6] at the end of the power - on -r eset time. 62 p2led0/ lebe ipu/o endian mode select for 8/16 - bit host interface nc or p ull?up (default) = little endian , p ull?down = big endian . this pin value is latched into register ccr, bit [10] at the end of the power - on -r eset time. note s: ipu/o = input with internal pull?up (58k 30%) during power?up/reset; output pi n otherwise. ipd/o = input with internal pull?down (58k 30%) during power? up/reset; output pin otherwise. all strap?in pins are latched during power?up or reset as well as re?strap?in when hardware/software power - down and hardware reset . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 30 revision 1.0 functional description the ksz8462hl/fhl is a highly - integrated networking device that incorporates a layer?2 switch, two 10bt/100bt physical layer transceivers (phys) and associated mac units, and a b us interface unit (biu) with one general 8/16?bit host interface, and key ieee 1588 precision time protocol (ptp) features. the ksz8462hl/fhl operates in a managed mode. in managed mode, a host processor can access and control all phy, switch, mac, and ieee 1588 related registers within the device via the host inter face. physical signal transmission and reception are enhanced through the use of analog circuits in the phy that make the design more efficient and allow for low power consumption. both power management and energy -e fficient e thernet (eee) are designed to save more power while device is in idle state. wake - on - lan is implemented to allow the ksz8462 to monitor the network for packets intended to wake up the system which is upstream from the ks z8462. the ksz8462hl/fhl is fully compliant to ieee802.3u standards. direction terminology readers should note that two different terminologies are used in this datasheet to describe the direction of data flow . in the standard terminology that is used for all micrel switches, direct ions are described from the point of view of the switch core: transmit indicates data flow out of the ksz8462 on any of the three ports, while receive indicates data flow into the ksz8462 . this terminology is used for the mib counters. when referencing the qmu block, which is located on port 3 between the internal mac and the external 8/16 - bit host interface, directions are revered C they are described from the point of view of the external host processor. thus, transmit indicates data flow from the host into port 3 of the ksz8462, while receive indicates data flow o ut of the ksz8462 on port 3. since both terminologies are used for port 3, it is important to note whether or not a par ticular section refers to the qmu. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 31 revision 1.0 physical (phy) block 100base ? tx transmit the 100base?tx transmit function performs parallel?to?serial conversion, 4b/ 5b coding, scrambling, nrz?to?nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel?to?serial conversion, which c onverts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz?to?nrzi format, and then transmitted in mlt3 cur rent output. an external 6.49k ? (1%) resistor for the 1:1 transformer ratio sets the output current. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp?pmd s tandard regarding amplitude balance, overshoot, and timing jitter. the wave?shaped 10base?t output driver i s also incorporated into the 100base?tx driver. 100base ? tx receive the 100bas e?tx receiver function performs adaptive equalization, dc restoration, mlt3?t o?nrzi conversion, data and clock recovery, nrzi?to?nrz conversion, de?scrambling, 4b/5b decoding, and serial?to?parallel conversion. the receiving side starts with the equalizat ion filter to compensate for inter?symbol interference (isi) over the twi sted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its characteristics to optimize performance. in this design, the variable equalizer makes an ini tial estimation based on comparisons of incoming signal strength against some known cable characteristics, and th en tunes itself for optimization. this is an ongoing process and self?adjusts against environmental chan ges such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc r estoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. t he differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de?scrambler followed by t he 4b/5b decoder. finally, the nrz serial data is converted to an mii format and provided as the input data to t he mac. scrambler/de ?s crambler (100base ?tx o nly) the purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagneti c interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11?bit wide linear f eedback shift register (lfsr). after the scrambler generates a 2047?bi t non?repetitive sequence, the receiver de?scrambles the incoming data stream using the same sequence as at the transmitter. pll clock synthesizer (recovery) the internal pll clock synthesizer generates 125mhz, 62.5mhz and 31.25mhz clock s for the ksz8462 system timing. these internal clocks are generated from an external 25mhz crystal or oscillator . refer to the device clocks section for more detailed information. 100base ? fx operation fiber mode is available only on the ksz8462fhl device. 100base?f x operation is similar to 100base?tx operation except that the scrambler/ de?scrambler and mlt3 encoder/decoder are bypassed on transmission and reception. in this fiber mode, the auto ? negotiation feature is bypassed and auto mdi/mdix is disabled since there is no standard that supports fiber auto ? negotiation and auto mdi/mdix mode. the fiber port must be forced to either full?duplex or half ?duplex mode. all ksz8462 devices are in copper mode (10 base - t / 100 base - tx) when reset or powered on. fiber mode is e nabled by clearing bits[ 7:6] in the cfgr register (0x0d8 - 0x0d9). each port is individually configurable. bit [13] in the dsp_cntrl_6 register (0x734 - 0x735) should also be cleared if either (or both) ports are set to fiber mode. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 32 revision 1.0 100base ? fx signal detection in 100base ? fx operation, the fiber signal detect input s ( fxsd ) are usually connected to the signal detect (sd ) output pin of the fiber transceiver. when fxsd is low , no fiber signal is detected and a far ? end fault (fef) is generated. when fxsd is high , the fiber signal is detected. to ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver sd output voltage swing to match the fxsd pins input vo ltage threshold . alternatively, the user may choose not to implement the fef feature. in this case, the fxsd input pin is tie d high to force 100base ? fx mode. in copper mode, and on the ksz8462hl, the fxsd pins are unused and should be pulled low. 100base ? fx far ? end fault a far?end f ault (fef) occurs when the signal detection is logically false on the receive side of the fiber transceiver. the KSZ8462FHLI detects a n fef when its fxsd input is below the f iber s ignal detect t hreshold . when an fef is detected, the KSZ8462FHLI signals its fiber link partner that a fef has occurred by sending 84 1s followed by a zero in the idle period between frames. by default, fef is enabled. fef can be disabled through register setting in p1cr4[12] and p2cr4[12]. 10base ? t transmit the 10base?t driver is incorporated with the 100base?tx driv er to allow for transmission using the same magnets. they are internally wave?shaped and pre?emphasized into outputs with typical 2. 3v amplitude. the harmonic contents are at least 27db below the fundamental frequency when driven by an all?ones manches ter? encoded signal. 10base ? t receive on the receive side, input buffers and level detecting squelch circuits are employed. a differential input receiver circuit a nd a phase?locked loop (pll) perform the decoding function. the manchester?encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signal s with levels less than 400mv or with short pulse widths to prevent noise at the rxp1 or rxm1 input from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8462 decodes a data frame. the receiver clock is maintained active during idle periods in between data recept ion. mdi/mdi ? x auto crossover to eliminate the need for crossover cables between similar devices, the ksz8462 supports hp?auto mdi/mdi?x and ieee 802.3u standard mdi/mdi?x auto crossover. hp?auto mdi/mdi?x is t he default. the auto?sense function detects remote transmit and receive pair s and correctly assigns the transmit and receive pairs for the ksz8462 device. this feature is extremely useful when end users are unaware of cable types in addition to saving on an additional uplink configuration connection. the auto?crossover feature can be disabled through the port control registers. the ieee 802.3u standard mdi and mdi?x definitions are noted in table 1 : table 1 . mdi/mdi - x pin definitions mdi mdi?x rj45 pins signals rj45 pins signals 1 td+ 1 rd+ 2 td? 2 rd? 3 rd+ 3 td+ 6 rd? 6 td? downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 33 revision 1.0 straight cable a straight cable connects an mdi device to an mdi?x device or an mdi?x device to an mdi device. figure 1 shows a typical straight cable connection between a network interface card (nic) and a switch, or hub (mdi?x). figure 1 . typical straight cable connection crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi?x d evice to another mdi?x device. figure 2 shows a typical crossover cable connection between two chips or hubs (two mdi?x devices). figure 2 . typical crossover cable connection downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 34 revision 1.0 auto?negotiation the ksz84 62 conforms to the auto ? negotiation protocol as described by ieee 802.3 . it allow s each port to operate at either 10 base ?t or 100 base ?tx. auto? negotiation allows unshielded twisted pair (utp) link partners to select the best common mode of operation. in auto ? negotiation , the link partners advertise capabilities across the link to each other and then compare their own capabilities with those they received from their link partners. the highest s peed and duplex setting that is common to the two link partners is selected as the mode of operation. auto - negotiation is also used to negotiate support for energy efficient ethernet (eee). auto - negotiation is supported only on the copper ports and not the fiber ports. the following list shows the speed and duplex ope rat ion mode from highest to lowest: ? highest: 100 base ? tx, full ? duplex ? high: 100 base ? tx, half?duplex ? low: 10 base ? t, full?duplex ? lowest: 10 base ? t, half?duplex if auto ? negotiation is not supported or the link partner to the ksz8462 is forced to bypass auto ? negotiation , the mode is set by observing the signal at the receiver. this is known as parallel mode because while the transmitter is sending auto ? negotiation advertisements, the receiver is listening for advertisements or a fixed signal protoco l. the link s etup is shown in figure 3 . figure 3 . auto negotiation and parallel operation downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 35 revision 1.0 linkmd ? cable diagnostics the ksz8462 linkmd ? uses time domain reflectometry (tdr) to analyze the cabling plant for c ommon cabling problems such as open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi and mdi?x pairs an d then analyzes the shape of the reflected signal. timing the pulse duration gives an indication of the distance t o the cabling fault with a maximum distance of 200m and an accuracy of 2m. internal circuitry displ ays the tdr information in a user?readable digital format in register p1scslmd[8:0] or p2scslmd[8:0]. note : c able diagnostics are only valid for copper connections . f iber?optic operation is not supported. access linkmd is initiated by accessing register p1scslmd (0x07c) or p2scslmd ( 0x094), the phy special control/status & linkmd register. usage before initiating linkmd, the value 0x8008 must be written to the ana_cntr l_3 register (0x74c C 0x74d). this needs to be done once (after power - on reset), but does not need to be repeated for each initiatio n of linkmd. auto - mdix must also be disabled before using linkmd. to disable auto - mdix, write a 1 to p1cr4[10] or p2cr4[10] to enable manual control over the pair used to transmit the linkmd pulse. the self - clearing cable diagnostic test enable bit, p1sc slmd[12] or p2scslmd[12], is set to 1 to start the test on this pair. when bit p1scslmd[12] or p2scslmd[12] returns to 0, the test is completed. t he test result is returned in bits p1scslmd[14:13] or p2scslmd[14:13] and the distance is returned in bits p1scslmd[8:0] or p2scslmd[8:0]. the cable diagnostic test results are as follows: 00 = valid test, normal condition 01 = valid test, open circuit in cable 10 = valid test, short circuit in cable 11 = invalid test, linkmd failed if p1scslmd[ 14:13] or p2scslmd[14:13] is 11, this indicates an invalid test, and it occurs w hen the ksz8462 is unable to shut down the link partner. in this instance, the test is not run, as it is not poss ible for the ksz8462 to determine if the detected signal is a reflection of the signal generated or a signal from another source. cable distance can be approximated by the following formula: p1scslmd[8:0] x 0.4m for port 1 cable distance p2scslmd[8:0] x 0.4m for port 2 cable distance this constant (0.4m) may be calibrated for different cabling conditions, including cables wit h a velocity of propagation that varies significantly from the norm. on ?c hip termination resistors the ksz8462 reduces board cost and simplifies board layout by using on?chip termination resistors for rx/tx differential pairs , eliminating the need for external termination resistors in copper mode. the on - chip termination and internal biasing will provide significant power savings when compared with using external biasing and term ination re sistors. loopback support the ksz8462 provides two loopback modes . o ne is n ear? end (remote) loopback to support remote diagnosing of failures on line side, and the other is far?end loopback to support local diagnosing of fai lures through all blocks of the device. in loopback mode, the speed of the phy port will be set to 100base?tx full?dup lex mode. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 36 revision 1.0 far ? end loopback far? end loopback is conducted between the ksz8462 s two phy ports. the loopback path starts at the o riginating phy ports receive inputs (rxp/rxm), wraps around at the loopback phy ports phy sical media dependent/physical media attachment ( pmd/pma ), and ends at the originating phy ports transmit outputs (txp/txm). bit[8] of registers p1cr4 and p2cr4 is used to enable far?end loopback for port s 1 and 2, respectively. as an alternative, bit[14] of registers p1mbcr and p2mbcr can be used to enable far?end loopbac k. the port 2 f ar? end l oopback path is illustrated in the figure 4 . near ? end (remote) loopback near?end (remote) loopback is conducted at either the port 1 phy or port 2 phy . the loopback path starts at the phy ports receive inputs (rxpx/rxmx), wraps around at the same phy ports pmd/pma (physical media dependent/physical media attachment) block, and ends at the same phy ports tr ansmit outputs (txpx/txmx). bit[1] of registers p1phyctrl and p2phyctrl is used to enable n ear? end loopback for port s 1 and 2, respectively. as an alternative, bit[9] of registers p1scslmd and p2scslmd can be used to enable n ear? end loopback. the n ear? end l oopback paths for port 1 and port 2 are illustrated in figure 4 . figure 4 . near - end and far - end loopback downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 37 revision 1.0 media access controller (mac) block mac operation the ksz8462 strictly abides by ieee 802.3 standards to maximize compatibility. additionally, there is an added mac filtering function to filter u nicast packets. the mac filtering function is useful in applications such as voip where restri cting certain packets reduces congestion and thus improves performance. address lookup the internal dynamic mac address lookup table stores mac addresses and their associated inform ation. it contains a 1k entry u nicast address learning table plus switching information. the ksz8462 is guaranteed to learn 1k addresses and distinguishes itself from hash?based lookup tables, which , depending on the operating environment and probabilities, may not guarantee the absolute number of addresses they can learn. learning the internal lookup engine updates the dynamic mac address table with a new entry i f the following conditions are met: ? the received packet's source address (sa) does not exist in the lookup table. ? the received packet has no receiving errors , and the packet size is of legal length. the lookup engine inserts the qualified sa into the table, along with the port number and time st amp. if the table is full, t he oldest entry of the table is deleted to make room for the new entry. migration the internal lookup engine also monitors whether a station has moved. if a station has moved, it updates the dynamic table accordingly. migration happens when the following conditions are met: ? the received packet's sa is in the table but the associated source port information is differ ent. ? the received packet has no receiving errors , and the packet size is of legal length. the lookup engine updates the existing record in the table with the new source port information. aging the lookup engine updates the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of tim e, the lookup engine removes the record from the table. the lookup engine constantly performs the aging process and continuously removes agin g records. the aging period is about 300 seconds , 75 seconds. this feature can be enabled or disabled through global r egister sgcr1[10]. forwarding the ksz8462 forwards packets using the algorithm that is depicted in the following flowcharts. figure 5 shows stage one of the forwarding algorithm where the search engine looks up the vlan id, static table, and dynamic table f or the destination address, and comes up with port to forward 1 (ptf1). ptf1 is then further modified by s panning tree, igmp snooping, port mirroring, and port vlan processes to come up with port to forward 2 (ptf2), as s hown in figure 6 . the packet is sent to ptf2. the ksz8462 will not forward the following packets: ? error packets: these include framing errors, frame check sequence (fcs) errors, alignment error s, and illegal size packet errors. ? ieee802.3x pause frames: ksz8462 intercepts these packets and performs full duplex f low control accordingly. ? "local" packets: based on destination address (da) lookup. if the destination port from the look up table matches the port from which the packet originated, the packet is defined as "local." downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 38 revision 1.0 figure 5 . destination address lookup flow chart in stage one downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 39 revision 1.0 figure 6 . destination address resolution flow chart in stage two downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 40 revision 1.0 inter packet gap (ipg) if a frame is successfully transmitted, then the minimum 96?bit time for ipg is measured between two consecutive packets. if the current packet is experiencing collisions, the minimum 96?bit time for ipg is measured from carrier sense (crs ) to the next transmit packet. back ? off algorithm the ksz8462 implements the ieee standard 802.3 binary exponential back?off algori thm in half?duplex mode. after 16 collisions, the packet is dropped. late collision if a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. legal packet size the ksz8462 discards packets less than 64 bytes and can be programmed to accept packet sizes up to 1536 bytes in sgcr2[1]. the ksz8462 can also be programmed for special applications to accept packet sizes up t o 2000 bytes in sgcr1[4]. flow control the ksz8462 supports standard 802.3x flow control frames in both transmit and receive directions . in the receive direction , if a pause control frame is received on any port , the ksz8462 will not transmit the next normal frame on that port until the timer, specified in the pause control frame, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new va lue in the second pause frame. during this period (while it is flow controlled), only flow control packets from the ks z8462 are transmitted. in the transmit direction , the ksz8462 has intelligent and efficient ways to determine when to invoke flow control and send pause frames . the flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues . the ksz8462 issues a pause frame containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the ksz8462 sends out another flow control frame with zero paus e time to turn off the flow control (turn on transmission to the port). a hysteresis feature is provided to prevent the flow control mec hanism from being constantly activated and deactivated. o n port 3, a flow control handshake exists internally between the qmu and the port 3 mac . in the qmu, there are three programmable threshold levels for flow control in the rxq fifo: 1) low water mark register fclwr (0x1b0), 2) high water mark register fchwr (0x1b2) , and 3) overrun water mark register fcowr (0x1b4). the qmu will send a pause frame internally to the mac when the rxq buffer fills with egress packets above the high water mark level (default 3.072 kb yte s available) , and a stop pause frame when the rxq buffer drops below the low water mark level (default 5.12 kb yte s available). the qmu will drop new packet s from the switch when the rxq buffer fills beyond the overrun water mark level (default 256 b yte s available). half ? duplex backpressure a half?duplex backpressure option (non?ieee 802.3 standard) is also provided. the activation and deactivation conditions are the same as in full?duplex mode. if backpressure is required, the k sz8462 sends preambles to defer the other stations' transmission (carrier sense deference). to avoid jabber and excessive deference (as defined in the 802.3 standard), after a certa in time, the ksz8462 discontinues the carrier sense and then raises it again quickly. this short silent time (no carr ier sense) prevents other stations from sending out packets thus keeping other stations in a carrier se nse deferred state. if the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are transmitted instead. if there are no additional packets to send, carrier sense ty pe backpressure is reactivated again until chip resources free up. if a collision occurs, the binary exponential back?of f algorithm is skipped and carrier sense is genera ted immediately, thus reducing the chance of further collision and carrier sense is maintai ned to prevent packet reception. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 41 revision 1.0 to ensure no packet loss in 10base?t or 100base?tx half?duplex mode, the user m ust enable the following bits: ? aggressive back off (bit[8] in sgcr1) ? no excessive collision drop (bit[3] in sgcr2) ? back pressure flow control enable (bit[11] in p1cr2/p2cr2) note : these bits are not set in default, since this is not the ieee standard. broadcast storm protection the ksz8462 has an intelligent option to protect the switch system from r eceiving too many broadcast packets. as the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resour ces (bandwidth and available space in transmit queues) may be utilized. the ksz8462 has the option to include multicast packets for storm control. the broadcast storm rate parameters are programmed globally, and c an be enabled or disabled on a per port basis in p1cr1[7] and p2cr1[7]. the rate is based on a 67ms interval for 100bt and a 670ms interval for 10bt. at the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts to count the number of bytes during the interval. the rate definition is described in sgcr3[2 :0][15:8]. the default setting is 0x63 (99 decimal). this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec 67 ms/interval x 1% = 99 frames/interval (approx.) = 0x63 note: 148,800 frames/sec is based on 64 ? byte block of packets in 100base ? t with 12 bytes of ipg and 8 bytes of preamble between two packets. port individual mac a ddress and source port filtering the ksz8462 can provide individual mac addresses for port 1 and port 2. they can be set at registers 0x0b0h - 0x0b5h a nd 0x0b6 - 0x0bb. received packets can be filtered (dropped) if their source address matches the mac address of port 1 or port 2. this feature can be enabled by setting bits[ 11:10] in the p1cr1 or p2cr1 registers. one example of usage is that a packet will b e dropped after it completes a full round trip within a ring network. address filtering function the ksz8462 supports 11 different address filtering schemes as shown in table 2 . the ethernet destination address (da) field inside the packet is the first 6?byte field which uses to compare wi th either the host mac address registers (0x110 C 0x115) or the mac address hash table registers (0x1a0 C 0x1a7) for address filtering operation. the first bit (bit[40]) of the destination address (da) in the ethernet packet decides whether this is a physica l address if bit[40] is 0 or a multicast address if bit[40] is 1. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 42 revision 1.0 table 2. mac address filtering scheme item address filtering mode receive control register (0x174 ? 0x175): rxcr1 description rx all (bit [4]) rx inverse (bit [1]) rx physical address (bit [11]) rx multicast address (bit [8]) 1 perfect 0 0 1 1 all rx frames are passed only if the da exactly matches the mac address in marl, marm and marh registers. 2 inverse perfect 0 1 1 1 all rx frames are passed if the da is not matching the mac address in marl, marm, and marh registers. 3 hash only 0 0 0 all rx frames with either multicast or physical destination address are filtering against the mac address hash table. 4 inverse hash only 0 1 0 0 all rx frames with either multicast or physical destination address are filtering not against the mac address hash table. all rx frames which are filtering out at item 3 (hash only) only are passed in this mode. 5 hash perfect (default) 0 0 1 0 all rx frames are passed with physical address (da) matching the mac address and to enable receive multicast frames that pass the hash table when multicast address is matching the mac address hash table. 6 inverse hash perfect 0 1 1 0 all rx frames which are filtering out at item 5 (hash perfect) only are passed in this mode. 7 promiscuous 1 1 0 0 all rx frames are passed without any conditions. 8 hash only with multicast address passed 1 0 0 0 all rx frames are passed with physical address (da) matching the mac address hash table and with multicast address without any conditions. 9 perfect with multicast address passed 1 0 1 1 all rx frames are passed with physical address (da) matching the mac address and with multicast address without any conditions. 10 hash only with physical address passed 1 0 1 0 all rx frames are passed with multicast address matching the mac address hash table and with physical address without any conditions. 11 perfect with physical address passed 1 0 0 1 all rx frames are passed with multicast address matching the mac address and with physical address without any conditions. notes: bit [0] (rx enable), bit [5] (rx unicast enable) and bit [6] (rx multicast enable) must set to 1 in rxcr1 register. the ksz8462 will discard frame with sa same as the mac a ddress if bit[0] is set in rxcr2 register . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 43 revision 1.0 switch block switching engine the ksz8462 features a high?performance switching engine to move data to and from the macs packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall latency. t he switching engine has a 32kbyte internal frame buffer. this resource is shared between all the ports. there are a total of 256 buffers available. each buffer is sized at 128 bytes. spanning tree support to support spanning tree, the host port is the designated port for the processor. the other ports ( port 1 and port 2) can be configured in one of the five spanning tree states via transmit enable, receive enable and learning disable register settings in registers p1cr2 and p2cr2 for port s 1 and 2, respectively. ta ble 3 shows the port setting and software actions taken for each of the five spanning tree states. table 3 . spanning tree states disable state port setting software action the port should not forward or receive any packets. learning is disabled. xmit enable = 0, receive enable = 0, learning disable = 1 the processor should not send any packets to the port. the switch may still send specific packets to the pro cessor (packets that match some entries in the static mac address table with overriding bit set) and the processor should discard those packets. addr ess learning is disabled on the port in this state. blocking state only packets to the processor are forwarded. xmit enable = 0, receive enable = 0, earning disable = 1 the processor should not send any packets to the port(s) in this state. the processor should program the static mac address table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should also be set so that the switch will forward those specific packets to the processor. address learning is disabled on the port in this state. listening stat e only packets to and from the processor are forwarded. learning is disabled. xmit enable = 0, receive enable = 0, learning disable = 1 the processor should program the static mac address table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processo r may send packets to the port(s) in this state. address learning is disabled on the port in this state. learning state only packets to and from the processor are forwarded. learning is enabled. xmit enable = 0, receive enable = 0, learning disable = 0 the processor should program the static mac address table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state. address learning is enabled on the port in this state. forwarding state packets are forwarded and received normally. learning is enabled. xmit enable = 1, receive enable = 1, learning disable = 0 the processor programs the static mac address table with the entries that it needs to receive (for example, bpdu packets). the overriding bit is set so that the switch forwards those specific packets to the processor. the processor can send packets to the port(s) in this state. address learning is enabled on the port in this state. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 44 revision 1.0 rapid spanning tree support there are three operational states assigned to each port for rstp (discarding, learning, and for warding): ? discarding ports do not participate in the active topology and do not learn mac addresses. ? discarding state: the state includes three states of the disable, blocking and listening of s tp. ? port setting: xmit enable = 0, receive enable = 0, learning disable = 1. discarding state software action: the host processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static table with overriding bit set) and the processor should discard those packets. when the ports learning capability (learning disable = 1) is di sabled, setting bits[ 10:9] in the sgcr8 register will rapidly flush the port related entries in the dynamic mac t able and static mac table. the processor is connected to port 3 via the host interface. address learning is disabled on the port in this state. learning state ports in learning states learn mac addresses, but do not forward user traffic. learning state: only packets to and from the processor are forwarded. learning is enabled. port setting for learning state: transmit enable = 0, receive enable = 0, learning di sable = 0. software action: the processor should program the static mac table with the entries t hat it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state (see tail tagging mode section for details.) address learning is enabled on the port in this state. ports in forwarding states fully participate in both data forwarding and mac learning. forwarding state forwarding state: packets are forwarded and received norma lly. learning is enabled. port setting: transmit enable = 1, receive enable = 1, learning disable = 0. software action: the processor should program the static mac table with the entries t hat it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the pr ocessor. the processor may send packets to the port(s) in this state, see tail tagging mo de section for details. address learning is enabled on the port in this state. rst p uses only one type of bpdu called rstp bpdus. they are similar to stp configura tion bpdus with the exception of a type field set to version 2 for rstp and version 0 for stp, and a flag field carrying additional information. tail tagging mode tail t ag mode is only seen and used by the port 3 host interface, which should be connected to a processor. it is an effective way to retrieve the ingress port information for spanning tree protocol, igmp snooping, and other applic ations . b it s [1:0] in the one byte tail tagging are used to indicate the source/destination port in port 3. b its [ 3:2] are used for priority setting of the ingress frame in port 3 . other bits are not used. the tail t ag feature is enabled by setting bit [8] in the sgcr8 register. figure 7 . tail tag frame format downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 45 revision 1.0 table 4 . tail tag rules ingress to port 3 (host ? > ksz8462 ) b it [1 : 0] destination port 00 normal (address look up) 01 port 1 10 port 2 11 port 1 and port 2 bit [3 : 2] frame priority 00 priority 0 01 priority 1 10 priority 2 11 priority 3 egress from port 3 (ksz8462 ? > host) b it [0] source port 0 port 1 1 port 2 igmp support for internet group management protocol (igmp) support in layer 2, the ksz8462 provides two components: igmp snooping the ksz8462 traps igmp packets and forwards them only to the processor (host port). the igmp packets are identified as ip packets (either ethernet ip packets, or ieee 802.3 snap ip pack ets) with ip version = 0x4 and protoco l version number = 0x2. multicast address insertion in the static mac table once the multicast address is programmed in the static mac address table , the multicast session is trimmed to the subscribed ports, instead of broadcasting to all ports. to enable igmp support, set bit[14] to 1 in the sgcr2 register. als o, tail tagging mode needs to be enabled, so that the processor knows which port the igmp packet was received on. this is ac hieved by setting bit[8] to 1 in the sgcr8 register. ipv6 mld snooping the ksz8462 traps ipv6 multicast listener discovery (mld) packets and forwards them only to the processor (host port). mld snooping is controlled by sgcr2, bit[13] (mld snooping enable) and sgcr2 bit[1 2] (mld option). setting sgcr2 bit[13] causes the ksz8462 to trap packets that meet all of the fo llowing conditions: ? ipv6 multicast packets ? hop count limit = 1 ? ipv6 next header = 1or 58 (or = 0 with hop?by?hop next header = 1 or 58) ? if sgcr2[12] = 1, ipv6 next header = 43, 44, 50, 51, or 60 (or = 0 with hop?by?hop next header = 43, 44, 50, 51, or 60) downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 46 revision 1.0 port mirroring support ksz8462 supports por t mirroring comprehensively as illustrated in the following sub - sections: receive only mirror - on -a- port all the packets received on the port are mirrored on the sniffer port. for example, port 1 is programmed to be receive sniff and the host port is programmed to be the sniffer port. a packet receiv ed on port 1 is destined to port 2 after the internal lo okup. the ksz8462 forwards the packet to both port 2 and the host port. the ksz8462 can optionally even forward bad received packets to the sniffer port. t ransm it only mirror - on -a- port all the packets transmitted on the port are mirrored on the sniffer port. for example, port 1 is programmed to be transmit sniff and the host port is programmed to be the sniffer port. a packet receiv ed on port 2 is destined to port 1 after the internal lookup. the ksz8462 forwards the packet to both port 1 and the host port. r ecei ve and transmit mirror - on - two -p orts all the packets received on port a and transmitted on port b are mirrored on the sniffer port. to turn on the and feature, set register sgcr2, bit 8 to 1. for example, port 1 is programmed to be receive sniff, port 2 is programmed to be transmit sniff, and the host port is programmed to be the sniffer port . a packet received on port 1 is destined to port 2 after the internal lookup. the ksz8462 forwards the packet to both port 2 and the host po rt. multiple ports can be selected as receive sniff or transmit sniff. in addition, an y port can be selected as the sniffer port. all these per port features can be selected through registers p1cr2, p2cr2, an d p3cr2 for port s 1, 2, and the host port, respectively. ieee 802.1q vlan support the ksz8462 supports 16 active vlans out of the 4096 possible vlans specified in the ieee 80 2.1q specification. ksz8462 provides a 16?entry vlan table, which converts the 12?bits v lan id (vid) to the 4?bits filter id (fid) for address lookup. if a non?tagged or null?vid?tagged packet is received, the ingres s port default vid is used for lookup. in vlan mode, the lookup process starts with vlan table lookup to determine whet her the vid is valid. if the vid is not valid , the packet is dropped and its address is not learned. if the vid is valid, the fid is retrieved for further lookup. the fid + destination address (fid+da) are used to determine the destination port. the fid + sour ce address (fid+sa) are used for address learning (see table 5 and table 6 ). advanced vlan features are also supported in the ksz8462 , such as vlan ingress filtering and discard non pvid defined in bits[ 14:13] of p1cr2, p2cr2 and p3cr2 registers. these features can be controlled on per port basis. table 5 . fid + da lookup in vlan mode da f ound in static mac table? use fid f lag? fid match? da+fid found in dynamic mac table? action no dont care dont care no broadcast to the membership ports defined in the vlan table bits[ 18:16] no dont care dont care yes send to the destination port defined in the dynamic mac address table bits[ 53:52] yes 0 dont care dont care send to the destination port(s) defined in the static mac address table bits[ 50:48] yes 1 no no broadcast to the membership ports defined in the vlan table bits[ 18:16] yes 1 no yes send to the destination port defined in the dynamic mac address table bits[ 53:52] yes 1 yes dont care send to the destination port(s) defined in the static mac address table bits[ 50:48] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 47 revision 1.0 table 6 . fid + sa lookup in vlan mode fid+sa found in dynamic mac table? action no learn and add fid+sa to the dynamic mac address table yes update time stamp qos priority support the ksz8462 provides quality - of - service (qos) for applications such as voip and video conferencing. the ksz8462 offer 1, 2, and 4 priority queues option per port . this is controlled by bit[0] and bit[8] in p1cr1, p2cr1 and p3cr1 registers as shown below: ? bit[0], bit[8] = 00 egress port is a single output queue as default. ? bit[0], bit[8] = 01 egress port can be split into two priority transmi t q ueues. (q0 and q1) ? bit[0], bit[8] = 10 egress port can be split into four priority transmit queues. (q 0 , q1, q2 and q3) the four priority transmit queues is a new feature in the ksz8462 . queue 3 is the highest priority queue and queue 0 is the lowest priority queue. if a port's transmit queue is not split, high priority and low priority packets have equal priority in the transmit queue. there is an additional option for every port via bits[15,7] in the p1 txqrcr1 , p1 txqrcr2 , p2txqrcr1, p2txqrcr2, p3txqrcr 1, and p3txqrcr2 registers to select either always to deliver high priority packets firs t or use weighted fair queuing for the four priority queues scale by 8:4:2:1. port?based priority with port?based priority, each ingress port is individually classifie d as a specific priority level. all packets received at the high?priority receiving port are marked as high priority and are sent to the hi gh?priority transmit queue if the corresponding transmit queue is split. bits [4:3] of registers p1cr1, p2cr1, and p3c r1 is used to enable port?based priority for port s 1, 2, and the host port, respectively. 802.1p?based priority for 802.1p?based priority, the ksz8462 examines the ingress (incoming) packets to det ermine whether they are tagged. if tagged, the 3?bit priori ty field in the vlan tag is retrieved and used to look up the priority mapping value, as specified by the register sgcr6. the priority mapping value is programmable. figure 8 illustrates how the 802.1p priority field is embedded in the 802.1q vlan tag. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 48 revision 1.0 figure 8 . 802.1p priority field format 802.1p based priority is enabled by bit[5]of registers p1cr1, p2cr1, and p3cr1 for port s 1, 2, and the host port, respectively. the ksz8462 provides the option to insert or remove the priority tagged frame's header at each individual egress port. this header, consisting of the 2 bytes vlan protocol id (vpid) and the 2 bytes tag cont rol information field (tci), is also referred to as the 802.1q vlan tag. tag insertion is enabled by bit [2] of registers p1cr1, p2cr1, and p3cr1 for port s 1, 2, and the host port, respectively. at the egress port, untagged packets are tagged with the ingress ports default tag. the default tags are programmed in register sets p1vidcr, p2vidcr, and p3vidcr for port s 1, 2, and the host port, respectively. the ksz8462 does not add tags to already tagged packets. tag removal is enabled by bit [1] of registers p1cr1, p2cr1, and p3cr1 for port s 1, 2, and the host port, respectively. at the egress port, tagged packets will have their 802.1q vlan tags removed. the ksz8462 will not m odify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re?mapping this is a qos feature that allows the ksz8462 to set the user priori ty ceiling at any ingress port. if the ingress packets priority field has a higher priority value than the default tags priority field of the ingress port, the packets priority field is replaced with the default tags priority field. the user priority ceiling is enabled by bit[3] of registers p1cr2, p2cr2, and p3cr2 for port s 1, 2, and the host port, respectively. diffserv - based priority diffserv?based priority uses the tos registers shown in the type - of - service (tos) priority control registers section. the tos priority control registers implement a fully - decoded, 128? bit differentiated services code point (dscp) register to determine packet priority from the 6?bit tos field in the ip header. when the most significant 6 bits of the tos field are fully decoded, the resultant of the 64 possibilities is compared with the corresponding bi ts in the dscp register to determine priority. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 49 revision 1.0 rate - limiting support the ksz8462 supports hardware rate limiting from 64kbps to 99mbps (refer to table 23 ), independently on the receive side and on the transmit side as per port basis. for 10 base ? t, a rate setting above 10mbps means the rate is not limited. on the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control registers. on the transmit side, the data transmit rate for each priority qu eue at each port can be limited by setting up egress rate control registers. the size of each frame has options to include minimum interfr ame gap ( ifg ) or p reamble byte, in addition to the data field (from packet da to fcs). for ingress rate limiting, ksz8462 provides options to selectively choose frames from all t yp es, multicast, broadcast, and flooded u nicast frames. the ksz8462 counts the data rate from those selected type of fr ames. packets are dropped at the ingress port when the data rate exceeds the specified rate limit. for egress rate limiting, the leaky b ucket algorithm is applied to each output priority queue for shaping output traffic. inter frame gap is stretched on a per frame base to generate smooth, non?burst egress traffic. the throughput of each output priority queue is limited by the egress rate sp ecified. if any egress queue receives more traffic than the specified egress rate throu ghput, packets may be accumulated in the output queue and packet memory. after the memory of the queue or the port is used up, packet dropping or flow control will be tr iggered. as a result of congestion, the actual egress rate may be dominated by flow control/dr opping at the ingress end, and may be therefore slightly less than the specified egress rate. to reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth. mac address filtering function when a packet is received, the destination mac address is looked up in both the static and dynamic mac ad dress tables. if the address is not found in either of these tables, then the destination mac address is unknown. by default, an unknown unicast packet is forwarded to all ports except the port at which it was rec eived. an optional feature makes it possible to specify the port or ports to which to forward unknown unicast pack ets. it is also possible to specify no ports, meaning that unknown unicast packets will be discarded. this feature is enabled by setting bit[7] in sgcr7. the u nicast mac address filtering function is useful in preventing the broadcast of u nicast packets that could degrade the quality of this port in applications such as voice - over - internet protocol (voip). downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 50 revision 1.0 queue management unit (qmu) the queue management unit (qmu) manages packet traffic on port 3 between the internal mac and the external host processor interface . it has built?in packet memory for receive and transmit functions cal led transmit queue (txq) and receive queue (rxq). the rxq capacity is 12k b ytes, and the txq capacity is 6k b ytes. these fifos support back?to?back, non?blocking frame transfer pe rformance. there are control registers for system control , frame status registers for current packet transmit/receive status, and interrupts to inform the host of the r eal time tx/rx status. please refer to the direction terminology section for a discussion of the different terminolog y used to describe the qmu. transmit queue (txq) frame format the frame format for the transmit queue is shown in table 7 . the first word contains the control information for the frame to transmit. the second word is used to specify the total number of bytes of the frame. the packet dat a follows. the packet data area holds the frame itself. it may or may not include the crc checksum depen ding upon whether hardware crc checksum generation is enabled in bit [1] in txcr register. multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory, thus avoiding overrun. for each transmitted frame, the transmit status information f or the frame is located in the txsr (0x172) register. table 7 . frame format for transmit queue packet memory address offset (bytes) bit 15 2 nd byte bit 0 1 st byte 0 control word (high byte and low byte need to swap in big?endian mode) 2 byte count (high byte and low byte need to swap in big?endian mode) 4 ? u p transmit packet data (m aximum size is 2000) since multiple packets can be pipelined into the tx packet memory for transmit, the transmit status reflects the status of the packet that is currently being transferred on the mac interface, which may or may n ot be the last queued packet in the tx queue. the transmit control word is the first 16?bit word in the tx packet mem ory, followed by a 16?bit byte count. it must be word aligned. each control word corresponds to one tx packet. table 8 gives the transmit control wo rd bit fields. table 8 . transmit control word bit fields bit description 15 txic transmit interrupt on completion : when this bit is set, the ksz8462 sets the transmit interrupt after the present frame has been transmitted. 14 ? 10 reserved. 9 ? 8 reserved 7 ? 6 reserved. 5 ? 0 txfid transmit frame id : this field specifies the frame id that is used to identify the frame and its associa ted status information in the transmit status register. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 51 revision 1.0 the transmit byte count specifies the total number of bytes to be transmitted from the tx q. its format is given in table 9 . table 9 . transmit byte count format bit description 15 ? 11 reserved. 10 ? 0 txbc transmit byte count : transmit byte count. hardware uses the byte count information to conserve the tx buffer memory for better utilization of the packet memory. note : the hardware behavior is unknown if an incorrect byte count information is written to this field. writing a 0 value to this field is not permitted. the data area contains six bytes of destination address (da) followed by six bytes of source address (sa), followed by a variable ?length number of bytes. on transmit, all bytes are provided by the cpu , including the source address. the ksz8462 does not insert its own sa. the ieee 802.3 frame length word (frame ty pe in ethernet) is not interpreted by the ksz8462. it is treated transparently as data both for transmit operations. frame transmitting path operation in txq this section describes the typical register settings for transmitting pack ets from a host processor to the ksz8462 using the generic bus interface. the user can use the default value for most of the transmit registers . table 10 describes all the registers which need to be set and used for transmitting single frames. t able 10 . register setting for transmit function block register name [bit](offset) description txcr[3:0](0x170) txcr[8:5](0x170) set transmit control function as below: set bit[3] to enable transmitting flow control. set bit [2] to enable transmitting padding. set bit[1] to enable transmitting crc. set bit [0] to enable transmitting block opera tion. set transmit checksum generation for icmp, udp, tcp and ip packet. txmir[12:0](0x178) the amount of free transmit memory available is represented in units of byte. the txq memor y (6 kbyte) is used for both frame payload and control word. txqcr[0](0x180) for single frame to transmit, set this bit[0] = 1 (manual enqueue). the ksz8462 will enab le current tx frame prepared in the tx buffer is queued for transmit; this is only transmit one frame at a time. note : this bit is self?clearing after the frame is finished transmitt ing. the software should wait for the bit to be cleared before setting up another new tx frame. txqcr[1](0x180) when this bit is written as 1, the ksz8462 will generate interrupt (bit[6] in the isr regi ster) to cpu when txq memory is available based upon the total amount of txq space requested by cpu at txntfsr (0x19e) register. note : this bit is self?clearing after t he frame is finished transmitting. the software should wait for the bit to be cleared before set to 1 again. rxqcr[3](0x182) set bit[3] to start dma access from host cpu either read (receive frame data) or w rite (transmit data frame) txfdpr[14](0x184) set bit[14] to enable txq transmit frame data pointer register increments automatical ly on accesses to the data register. ier[14][6](0x190) set bit[14] to enable transmit interrupt in interrupt enable r egister . set bit[6] to enable transmit space availab le interrupt in interrupt enable r egister. isr[15:0](0x192) write all ones (0xffff) to clear all interrupt status bits after interrupt occurred in interrupt enable r egister. txntfsr[15:0](0x19e) the host cpu is used to program the total amount of txq buffer space which is required for next total transmit frames size in double?word count. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 52 revision 1.0 driver routine for transmitting packets from host processor to ksz8 462 the transmit routine is called by the upper layer to transmit a contiguous block of data throug h the ethernet controller. it is the users choice to decide how the transmit routine is implemented. if the et hernet controller encounters an error while transmitting the frame, its the users choice to decide whether the dri ver should attempt to retransmit the same frame or discard the data. figure 9 shows the step?by?step process for transmitting a single packet from host processor to the ksz8462. each dma write operation from the host cpu to the write txq frame buffer begins with writing a control word and a byte count of the frame header. at the end of the write, the host cpu must write each piece of fr ame data to align with a double word boundary at the end. for example, the host cpu has to write up to 68 bytes if the transmit frame is 65 bytes. host receives an ethernet pkt from upper layer and prepares transmit pkt data (data, data_length, frame id and destination port). the transmit queue frame format is shown in table 7 check if ksz8462hl txq memory size is available for this transmit pkt? (read txmir reg) write an 1 to rxqcr[3] reg to enable txq write access, then host starts write transmit data (control word, byte count and pkt data) to txq memory. this is moving transmit data from host to ksz8462hl txq memory until whole pkt is finished write an 0 to rxqcr[3] reg to end txq write access write an 1 to txqcr[0] reg to issue a transmit command (manual- enqueue) to the txq. the txq will transmit this pkt data to the phy port option to read isr[14] reg, it indicates that the txq has completed to transmit at least one pkt to the phy port, then write 1 to clear this bit yes no write the total amount of txq buffer space which is required for next transmit frame size in double-word count in txntfsr[15:0] register set bit 1=1 in txqcr register to enable the txq memory available monitor wait for interrupt and check if the bit 6=1 (memory space available) in isr register ? yes no figure 9 . host tx single frame in manual enqueue flow diagram downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 53 revision 1.0 receive queue (rxq) frame format the frame format for the receive queue is shown in tab le 11 . the first word contains the status information for the frame received. the second word is the total number of bytes of the rx frame. following that is the packet data area. the packe t data area holds the frame itself. it includes the crc checksum. table 11 . frame format for receive queue packet memory address offset (bytes) bit 15 2 nd byte bit 0 1 st byte 0 status word (high byte and low byte need to swap in big?endian mode. also see description in rxfhsr register) 2 byte count (high byte and low byte need to swap in big?endian mode. also see description in rxfhbcr register) 4 ? u p receive packet data (maximum size is 2000) frame receiving path operation in rxq this section describes the typical register settings for receiving packets from ksz8462 t o the host processor via the generic host bus interface. user s can use the default value for most of the receive registers. table 12 describes all registers which need to be set and used for receiving single or multiple frames. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 54 revision 1.0 table 12 . register settings for receive function block re gister name [bit](offset) description rxcr1 (0x174) rxcr2 (0x176) set receive control function as below: set rxcr1[10] to enable receiving flow control. set rxcr1[0] to enable receiving bloc k operation. set receive ch ecksum check for icmp, udp, tcp, and ip packet. set receive address filtering scheme as shown in table 2 . rxfhsr[15:0] (0x17c) this register (read only) indicates the current received frame header status informati on. rxfhbcr[11:0] (0x17e) this register (read only) indicates the current receive d frame header byte count information. rxqcr[12:3] (0x182) set rxq control function as below: set bit[3] to start dma access from host cpu either read (receive frame data) or w rite (transmit data frame). set bit[4] to automatically enable rxq frame buffer de?queue. set bit[5] to enable rx frame count threshold and read bit[10] for status. set bit[6] to enable rx data byte count threshold and read bit[11] for status. set bit[7] to enable rx frame duration timer threshold and read bit[12] for status. set bit[9] to enable rx ip header two?byte offset. rxfdpr[14] (0x186) set bit[14] to enable rxq address register increments automatically on accesses to the data r egister. rxdttr[15:0] (0x18c) used to program the received frame duration timer value. when rx frame duration in rxq exceeds thi s threshold in 1us interval count and bit[7] of rxqcr register is set to 1, the ksz8462 wil l generate rx interrupt in isr[13] and indicate the status in rxqcr[12]. rxdbctr[15:0] (0x18e) used to program the received data byte count value. when the number of received bytes in rxq exceeds this threshold in byte count and bit [6] of rxqcr register is set to 1, the ksz8462 w ill generate rx interrupt in isr[13] and indicate the status in rxqcr[11]. ier[13] (0x190) set bit[13] to enable receive interrupt in interrupt enable register . isr[15:0] (0x192) write all ones (0xffff) to clear all interrupt status bi ts after interrupt occurred in interrupt status r egister. rxfc[15:8] (0x1b8) rx frame count. this indicate s the total number of frames received in the rxq frame buffer when the r eceive i nterrupt (reg. isr, bit [13] ) occurred. rxfctr[7:0] (0x19c) used to program the received frame count threshold value. when the number of received frames in rx q exceeds this threshold value and bit[5] of rxqcr register is set to 1, the ksz8462 will generate an rx interrupt in isr[13] and indicate the status in rxqcr[10]. driver routine for receiving packets from the ksz8462 to the host pro cessor the software driver receives data packet frames from the ksz8462 device either as a result of polling or an interrupt based service. when an interrupt is received, the operating system invokes the interrupt service routin e that is in the interrupt vector table. if your system has operating system support, to minimize interrupt lockout time, the inter rupt service routine should handle at interrupt level only those tasks that require minimum execution time, such as error checking or device status change. the routine should queue all the t ime?consuming work to transfer the packet from the ksz8462 rxq into syst em memory at task level. figure 10 shows the step?by?step for receive packets from ksz8462 to host processor. note: for each dma read operation from the host cpu to read the rxq frame buf fer, the first read data (byte in 8?bit bus mode, word in 16?bit bus mode) is dummy data and must be discarded by the host cpu. afterward, the host cpu must read each data frame to align it with a double word boundary at the end. for example, the host cpu has to read up to 68 bytes if the number of received frames is 65 bytes. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 55 revision 1.0 figure 10 . host rx single or multiple frames in auto - dequeue flow diagram in order to read received frames from rxq without error, the software driver must follo w these steps: 1. when a receive interrupt occurs and the software driver writes a 1 to clear the rx interrupt in the isr register; the ksz8462 will update the rx frame counter (rxfc) register for this interrupt. 2. when the software driver reads back the rx fr ame count (rxfc) register, the ksz8462 will update both the receive frame header status and byte count r egisters (rxfhsr/rxfhbcr). 3. whe n the software driver reads back both the receive frame header status and byte count r egisters (rxfhsr/rxfhbcr), the ksz8462 will update the next r eceive f rame h eader s tatus and b yte c ount registers (rxfhsr/rxfhbcr). downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 56 revision 1.0 ieee 1588 precision time protocol (ptp) block the ieee 1588 precision time protocol (ptp) provides a method for establishin g synchronized time across nodes in an ethernet networking environment. the ksz8462 implements v2 (2008) of the ieee 1588 ptp specification. the ksz8462 3?port switch impl ements the ieee 1588 ptp version 2 protocol. port 1 and port 2 can be programmed as either end - to - end ( e2e ) or peer - to - peer ( p2p ) transparent clock (tc) ports . i n addition , port 3 can be programmed as either slave or master ordinary clock (oc) port. ingress timestamp capt ure, egress timestamp recording, correction field update with residence time and link delay, delay turn?around time insertion, egress timestamp insertion, and checksum update are supported. ptp frame filtering is implemented to enhance overall system performance. delay adjustments are implemented to fine tune the synchronization. versatile event trigger outputs and timestamp capture inputs are implemented to meet various real time application requirements through gpio pins. the key features of the ksz8462 implementation are as follows: ? both one?step and two?step tc operations are supported ? implementation of precision time clock per specification (upper 16 bits of second clock not implemented due to practical values of time) ? both e2e and p2p tc are supported on port 1 and port 2 ? both s lave and master oc are supported on port 3 ? ptp m ulticast and u nicast frames are supported ? transports of ptp over ipv4/ipv6 udp and ieee 802.3/ethernet are supported ? both p ath d elay request?response and peer delay mechanism are supported ? precision time stamping of input signals on the gpio pins ? creation and delivery of clocks, pulses, or other unique serial bit streams on the gpio pins with respect to precise precision time clock time. ieee 1588 defines two essential functions: the measurement of link and residence (switching) del ays by using the delay_req/resp or pdelay_req/resp messages, and the distribution of time information by using the sync/follow_up messages. the 1588 ptp event messages are periodically sent from the g rand m aster(s) in the network to all slave clock devices. link delays are measured by each slave node to all its link partners to compensate for the delay of ptp messages sent through the network . the 1588 ptp announce messages are periodically sent from the grandmaster(s) in the network to all slave clock devices. this information is then used by each node to select a master clock using the best master algorit hm available. 1588 ptp (version 2) defines two types of messages; event and general messages. thes e are summarized below and are supported by the ksz8462: event messages (an accurate timestamp is generated at egress and ingress): ? sync (from master to slave) ? delay_req (from slave to master) ? pdelay_req (between link partners for peer delay measurement) ? pdelay_resp (between link partners for peer delay measurement) general messages: ? follow_up (from master to slave) ? de lay_resp (from master to slave) ? pdelay_resp_follow_up (between link partners for peer delay measurement) ? announce ? management ? signaling downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 57 revision 1.0 ieee 1588 ptp clock types the ksz8462 supports the following clock types: ? ordinary c lock (oc) is defined as a ptp clock with a single ptp port in a ptp domain. it may serve as a source of time such as a master clock, or it may be a slave clock which synchronizes to another master cl ock. ? end - to - end transparent clock (e2e tc) is defined as a transparent clock that supports th e use of the end?to?end delay measurement mechanism between a slave clock and the master clock. in this method, the e2e t c intermediate devices do not need to be synchronized to the master clock and the end slave node is directly synchroni zed to the master clock. the e2e tc/sc slave intermediate devices can also be synchronized to the master clock. note that the transparent clock is not a real clock that can be viewed on an oscilloscope but rather it is a mec hanism by which delay are accounted for when transporting information across and through physical network nodes. ? peer - to - peer transparent clock ( p2p tc for version 2) is defined as a transparent clock, in addition to providing ptp event transit time information. p2p tc also provides corrections for the propagation del ay between nodes (link partners) by using pdelay_req ( p eer delay request) and pdelay_resp ( p eer delay response). in this method, the p2p tc intermediate devices can be synchronized to the master clock. a transparent clock (tc ) is not part of the master?slave hierarchy. instead, it measures the resident time which i s the time taken for a ptp message to traverse the node. the p2p tc then provides this information to the clock receiving the ptp message. in a ddition, the p2p tc measures and passes on the link delay of the receiving ptp message. note that the transparent clock is not a real clock that can be viewed on an oscilloscope but rather it is a mechanism by which delay are acc ounted for when transporting information across and through physical network nodes. ? master c lock is defined as a clock which is used as the reference clock for the entire system. the ksz8462 can operate as a master clock if needed. however, the quality of the clock signal will be limited by the quality of the crystal or oscillator used to clock the device. note : p2p and e2e tcs cannot be mixed on the same communication path. ieee 1588 ptp one?step or two?step clock operation the ksz8462 supports either 1?step or 2?step clock operation. ? one?step clock operation : a ptp mes sage (sync) exchange that provides time information using a single event message which eliminates the need for a follow_up message to be sent. this one? step operation will eliminate the need for software to read the timestamp and to send a follow_up messag e. ? two?step clock operation : a ptp messages (sync/follow_up) that provides time information using the combination of an event message and a subsequent general message. the follow_up message carries a precise estimate of the time the sync message was placed on the ptp communication path by the sending node . ieee 1588 ptp best master clock selection the ieee 1588 ptp specification defines an algorithm based on the characteristics of the clocks and s ystem topology called best master clock (bmc) a lgorithm. bmc uses a nnounce messages to establish the synchronization hierarchy. the algorithm compares data from two clocks to determine the better clock. each clock device continuous ly monitors the announce messages issued by the current master and compares the dataset to itself. the software controls this process. ieee 1588 ptp system time clock the system time clock (stc) in ksz8462 is a readable or writable ti me source for all ieee 1588 ptp related functions and contains three counters: a 32? bit counter for s econds, a 30? bit counter for n anos econds and a 32? bit counter for s ub? n anoseconds (units of 2 ?32 ns). refer to figure 11 whic h shows the precision time protocol c lock. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 58 revision 1.0 figure 11 . ptp system clock overview the stc is clocked (incremented by 40ns or updated with sub ns carry info) every 40ns by a derivative of the 125mhz derived clock. the 30?bit nanosecond counter will be numerically incremented by 39ns, 40ns, or 41ns every 40ns. there is another 3?bit phase counter that is designed to indicate one of the five sub phases (0ns, 8ns, 16ns, 24ns or 32ns) within the 40ns period. this provides finer resolution for the various messages and timestamps. the ov erflow for the 30? bit n anosecond counter is 0x3b9aca00 (109) and the overflow for the 32? bit s ub? n anosecond counter is 0xffffffff. th e system time clock does not support the upper 16?bits of the seconds field as def ined by the ieee 1588 ptp version 2 which specifies a 48?bit seconds field. if the 32?bit seconds counter overflo ws, it will have to be handled by software. note that an over flow of the seconds field only occurs every 136 years. the seconds value is kept track of in the ptp_rtc_sh and ptp_rtc_sl registers (0x608 C 0x60b). the nanoseconds value is kept track of in the ptp_rtc_nsh and ptp_rtc_nsl registers (0x604 C 0x607). the ptp_rtc_phase clock register (0x60c C 0x60d) is initialized to zero whenever the local processor writes to the ptp_rtc_nsl, ptp_rtc_nsh, ptp_rtc_sl, or ptp_rtc_sh registers. during normal operation when the stc clock is keeping synchronized real time, and not while it is undergoing any initialization manipulation by the processor to get it close to the real time, the p tp_rtc_phase clock register will be reset to zero at the beginning of the current 40ns stc clock update interval. i t will start counting at zero at the beginning of the 40ns period and every 8ns it will be incremented. the information provi ded by the ptp_rtc_phase register will increase the accuracy of the various timestamps and stc clock readings. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 59 revision 1.0 updating the system time clock the ksz8462 provides four mechanisms for updating the system time clock , specifically : ? directly set the time ? step time adjustment ? continuous time adjustment ? temporary time adjustment directly setting or reading the time directly setting the system time clock to a value is accomplished by setting a new tim e in the real time clock registers (ptp_rtc_sh/l, ptp_rtc_nsh/l and ptp_rtc_phase) and then setting the lo ad ptp 1588 clock bit (ptp_load_clk) . directly reading the system time clock is accomplished by setting the read ptp 1588 clock bit (ptp_read_clk). to avoid lower bits overflowing during reading the system time clock, a snapshot register technique is used. the value in the system time clock will be saved into a snapshot register by setting t he ptp_read_clk bit in ptp_clk_ctl, and then subsequent reads from ptp_rtc_s, ptp_rtc_ns, and ptp_rtc_phase will return t he system time clock value. the cpu will add the ptp_rtc_phase value to ptp_rtc_s and ptp_rtc _ns to get the exact real time . step time adjustment the system time clock can be incremented in steps if desired. the nanosecond value (ptp_rtc_nsh/l) can be added or subtracted when the ptp_step_adj_clk bit is set. the value wil l be added to the s ystem time clock if this action occurs while the ptp_step_dir bit = 1. the value will be subtrac ted from the system time clock if this action occurs while the ptp_step_dir bit = 0. the ptp_step_adj_clk bit is self?clearing. continuous time adjustment t he system can be set up to perform continuous time adjustment to the 1588 ptp clock. this is t he mode that is anticipated to be used the most. this mode is overseen by the local processor and provides a method of peri odically adjusting the count of the ptp clock to match the time of the master clock as best as possible. the rate registers (ptp_sns_rate_h and ptp_sns_rate_l) (0x610 C 0x613) are used to provide a value by which the sub nanosecond portion of the clock is adjusted on a periodic basis. while con tinuous adjustment mode ( ptp_continu_adj_clk = 1) is se lected, every 40ns the sub - nano second value of the clock will be adjusted in either a positive or negative direction as determined by the ptp_rate_dir bit. the value will be positi vely adjusted if pt p_rate_dir = 0 or negatively adjusted if ptp_rate_dir = 1. the rate adjustment al lows for correction with resolution of 2 ?32 ns for every 40ns reference clock cycle , and it will be added to or subtracted from the system time clock on every reference clock cycle right after the write to ptp_snc_rate_l i s done. to stop the continuous time adjustment, one can either set the ptp_continu_adj_clk = 0 or the ptp_sns_rate_h/ l value to zero. temporary time adjustment this m ode allows for the continuous time a djustment to take place over a specified period of time only. the period of time is specified in the ptp_adj_dura_h/l registers. this mode is enabled by setti ng the ptp_temp_adj_clk bit to one. once the duration is reached, the increment or decrement will cease. when the temporary time adjustment is done, the internal duration counter register (ptp_adj_dura_h/l) will stay at zero, whi ch will disable the time adjustment. the local processor needs to set the ptp_temp_adj_clk to one again to start another temporary time adjustment with the reloaded value into the internal rate and duration registers. the ptp_adj_dura_l r egister needs to be programmed before ptp_adj_dura_h register. the ptp_adj_dura_l, ptp_adj_dura_h and ptp_s ns_rate_l registers need to be programmed before the ptp_sns_rate_h register. the temporary time adjustment will star t after the ptp_temp_adj_clk bit is set to one. this bit is self - cleared when the adjustment is completed. software can read this bit to check whether the adjustment is still in progress. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 60 revision 1.0 ptp clock initialization during software initialization when the device is powering up, the ptp clock needs to be initialized in preparation for synchronizing to the master clock. the suggested order of tasks is to reset the ptp 1588 cloc k ( reset_ptp_clk = 0), load the ptp 1588 clock (ptp_load_clk = 1) with a value then enable the ptp 1588 clock (en_ptp_c lk = 1). during the initial synchronization attempt, the system time clock may be a little f ar apart from the ptp master clock, so it most likely will require a step time adjustment to get it closer. after that, the continuous time adjustment method or temporary time adjustment method may be the best options when the system time cl ock is close to being synchronized with the master c lock. more details on the 1588 ptp system time clock controls and functions can be found in the register de scriptions for registers 0x600 to 0x617. ieee 1588 ptp message processing the ksz8462 supports ieee 1588 ptp time synchronization when 1588 ptp mode and m essage detection are enabled in the ptp_msg_cfg_1 register (0x620 C 0x621). different operations will be applied to ptp packet processing based on the setting of p2p or e2e in transparent clock mode for port 1 and port 2, master or slave in ordinary clock mode for port 3 (host port), one?step or two?step clock mode, and if the domain checking is enab led. for the ipv4/udp egress packet, the checksum can be updated by either re?calculating the two?byt es or by setting it to zero. for the ipv6/udp egress packet, the checksum is always updated. all these 1588 ptp configurati on bits are in the ptp_msg_cfg_1/2 registers (0x620 C 0x623). for a more detailed description of the 1588 ptp message processing control and function, please refer to the register description s in the register map at locations 0x620 to 0x68f. ieee 1588 ptp ingress packet processing the ksz8462 can detect all ieee 802.3 ethernet 1588 ptp packets, ipv4/udp 1588 ptp packets, and ipv6/udp 1588 ptp packets by enabling these features in the ptp_msg_cfg_1 register (0x620 C 0x621). upon detection of receiving a 1588 ptp packet, the device will capture the receive timestamp at the time when the start - of - frame d elimiter (sfd) is detected . a djust ing the receive timestamp with the receive latency or the asymmetric delay is the responsibility of the software. the hardware only takes these values into consideration when it updates the correction field in t he ptp message header. likewise, the software needs to adjust the transmit timestamp with the transm it latency. both the ingress timestamp and the ingress port number will be embedded in the reserved fields of the 1588 ptp header. the embedded information will be used by the host to designate the destination port in the r esponse egress packet, identify the direction of the master port, and to calculate the link delay and offset. the 1588 ptp packet will be discarded if the 1588 ptp domain field does not match the domain number in th e ptp_domain_ver register (0x624 C 0x625) or if the 1588 ptp version number does not match version number (either 1 or 2) in the ptp_domain_ver register (0x624 C 0x625). packets with a version number of one will always be forwarded to port 1 or port 2, and not to port 3. the 1588 ptp packets that are not associated with packet messages in pairs (pdelay_ req with pdela y_resp, sync with follow_up, delay_req with delay_resp) can be filtered and not forwarded to port 3 if the corresponding enable bits are set in the ptp_msg_cfg_2 register (0x0622 C 0x623). the 1588 ptp version?1 packet will be forwarded without being modified. ieee 1588 ptp egress packet processing the ingress timestamp, the transport type of the 1588 ptp packet, the packet type (tagged or untagged), and the type of correction field update on the egress side are in the frame header and are accessible for modification by the egress logic in local switch packet memory. the 1588 ptp packet will be put in the egress queue of highest priority. from the 1588 ptp frame header inside the switch packet memory, the egress logic will get the correction field update instruction. the residence time, link delay in the ptp_p1/2_link_dly registers (0x646 C 0x647 and 0x666 C 0x667) or turn?around time might be added to the correction field depending upon the type of 1588 ptp egress packet. the 1588 ptp packet received from port 3 (host port) has the destination port information to forward as well as the timestamp information that will be used for updating the correction field in one?step clock operation. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 61 revision 1.0 this embedded information (in the reserved fields of 1588 ptp frame header) will be zero e d out before the egress packet is sent out to conform to the 1588 ptp standard. for one?step operation, the original times tamp will be inserted into the sync packet. the egress timestamp of the sync packet will be latched in the p1/2_sync_ts registers (0x64c C 0x64f and 0x66c C 0x66f), the egress timestamps of delay_req, pdelay_req and pdelay_resp will be latched in the p1/2_xdly_req_ts (0x648 C 0x64b and 0x668 C 0x6b) and p1/2_pdly_resp_ts registers (0x650 C 0x653 and 0x670 C 0x673). these latched egress timestamps will generate an interrupt to the host cpu and set the interrupt status bits in the ptp_ts_is register (0x68c C 0x68d) if the interrupt enable is set in the ptp_ts_ie register (0x68e C 0x68 f). these captured egress timestamps will be used by the 1588 ptp software for link delay measurement, offset adjustment, and time calculation. the transmit delay value from the port 1 or port 2 timestamp reference point to the network connection point in the ptp_p1/2_tx_latency registers (0x640 C 0x643) will be added to these value in the p1/2_sync_ts, p1/2_xdly_req_ts and p1/2_pdly_resp_ts registers to get the egress timestamp w ith reference point to the network connection point. for transmit delay_req or pdelay_req packets, the value in the ptp_p1/2_asym_cor registers (0x644 C 0x645 and 0x664 C 0x665) will be subtracted from the correction field. ieee 1588 ptp event triggering and timestamping a n event t rigger output signal can be generated when the target and activation time matches the ieee1588 ptp system clock time. likewise, an event timestamp input can be captured from an external event input signal and the corresponding time on the ieee1588 ptp system clock will be captured. up to seven gpio pins can be configured as either output signal when trigger target time is matching ieee 1588 ptp system clock time or monitoring input signal for external event timestamp. all tr igger outputs are generated by comparing the system clock time with trigger target ti me continuously to make sure time synchronization is always on?going. ieee 1588 ptp trigger outputs the ksz8462 supports up to 12 trigger output units which can output to any one of the seven gpio pins by setting bits[3:0] in trig[1:12]_cfg_1 registers. multiple trigger output units can be assigned to a single gpio pin at the same time as logical ored function allowing generation of more complex waveforms. also mul tiple trigger units can be c ascaded (one unit only at any time) to drive a single gpio pin to generate a long and repeata ble bit sequence. each trigger unit that is cascaded can be any signal type (edge, pulse, periodic, register - bits, and clock output). each trigger output u nit can be programmed to generate one time rising or falling edge (toggle mode), a single positive or negative pulse of programmable width, a periodic signal of programmable width, cycl e time, bit?patterns to shift out from trig[1:12]_cfg_[1:8] registers, and each trigger unit can be programmed to generate interrupt of trigger output u nit done and status in ptp_trig_ie/is registers. for each trigger unit, the host cpu programs t he desired output waveform, gpio pins, target time in trig[1:12]_tgt_ns and trig[1:12]_tgt_s regist ers that the activity is to occur, and enable the trigger output unit in trig_en register, then the trigger output signal will be generat ed on the gpio pin when the internal ieee 1588 ptp system time matches the desired target time. the dev ice c an be programmed to generate a pulse?per?s econd (pps) output signal. the maximum trigger output signal frequency is up to 12.5 mhz. for a more detailed description of the 1588 ptp trigger output control, configuration and functi on, please refer to the registers description in the register map from 0x200 to 0x397 locations. ieee 1588 ptp event timestamp input external event inputs on the gpio pins can be monitored and time - stamped with the resolution of 8ns. the external signal event can be monitored and detected as either rising edge, falling edge, positive pulse, or negative pulse by setting bits[7:6] in ts[1:12]_cfg registers. multiple timestamp input units can be cascaded or chained together to associate with a single gpio pin to detect a series of events. when event is detected, the timestamp will be captur ed in three fields: 32?bit second field in ts[1:12]_smpl1/2_sh/l registers, 30?bit nanosecond field in ts[1:12]_smpl1/2_nsh/l registers, and 3?bit phase field in ts[1:12]_smpl1/2_sub_ns registers. s econd and nanosecond fields are updated every 25 mhz clock cycle. the 3?bit p hase field is updated every 125mhz clock cycle and indicates one of the five 8 nanosecond/125 mhz clock cycles. the bit [14] in ts[1:12]_smpl1/2_nsh registers indicates the event timestamp input is either falling edge or rising edge. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 62 revision 1.0 the ksz8462 supports up to 12 timestamp input u nit s which can input from any one of the seven gpio pins by setting bits[11:8] in ts[1:12]_cfg registers. the enable bits[ 11:0] in ts_en register are used to enable the trigger output u nit s. the last timestamp input unit (unit 12) can support up to eight timestamps for multiple event detection and up to four pulses can be detected. the rest of the units (units 1?11) have two timestamps to support single edge or pulse detection. pulse width can be measured by the time difference between consecutive timestamps. w hen an input event is detected, one of the bits[ 11:0] in ts_rdy register is asserted and will generate a timestamp interrupt if the ptp_ts_ie bit is set. the host cpu is also expected to read the timestamp status in the ts[1:12 ]_status registers to report the number of detected event (either rising or falling edge) counts and overflow. in single mode, it can detect up to 15 events at any single unit. in cascade mode, it can detect up to two events at units 1?11 or up to 8 events at unit 12, and it can detect up to 15 events for any unit as a tail unit. pulses or edges can be detected up to 25 mhz. for more details on 1588 ptp event timestamp input control, configuration and function, pl ease refer to the register descriptions for locations 0x400 to 0x5fd in the register map. ieee 1588 ptp event interrupts all ieee 1588 ptp event trigger and timestamp interrupts are located i n the ptp_trig_ie/ptp_ts_ie enable registers and the ptp_trig_is/ptp_ts_is status registers. these interrupts are fully m askable via their respective enable bits and shared with other interrupts that use the intrn interrupt pin. these 12 trigger output status interrupts are logical ored together and connected to bit[10] i n the isr register. these 12 trigger output enable interrupts are logical ored together and connected to bit[10] in the ier register. these 12 timestamp status interrupts are logical ored together with the rest of bits in th is register and the logical ored output is connected to bit [2] in the isr register. these 12 timestamp enable interrupts are logical ored together with the rest of bits in this regi ster and the logical ored output is connected to bit[12] in the ier register. ieee 1588 gpio the ksz8462 supports seven gpio pins that can be used for general i/o or can be configured to utilize the timing of the ieee 1588 protocol. the se gpio pins can be used for input event monitoring, outputting pulses, outputting clocks, or outputting unique serial bit streams. the gpio output pins can be configured to initiate their output upon the occurrence of a specific time which is being kept by the onboard precision time c lock . likewise, the specific time of arrival of an input event can be captured and recorded with respect to the precision time c lock. refe r to the general purpose and ieee 1588 input/outpu t (gpio) section for details on the operation of the gpio pins. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 63 revision 1.0 general purpose and ieee 1588 input/output (gpio) overview the ksz8462 devices incorporate a set of general purpose input/output (gpio) pins that are conf igurable to meet the needs of many applications. the input and output signals on the gpio pins can be directly control led via a local processor or they can be set up to work closely with the ieee 1588 protocol to create and/or monitor precisely timed signals which are synchronous to the precision time clock. some gpio pins are dedicated , while others are dual function pins . dual function pins are managed by the iomxsel register . tab le 13 provides a convenient summary of available gpio resources in the ksz8462 devices. table 13 . ksz8462 gpio pin resources ksz8462 gpio pin# function gpio_0 48 gpio0 gpio_1 49 gpio1 gpio_2 52 gpio2 gpio_3 53 eesk (default) / gpio3 gpio_4 54 eedio (default) / gpio4 gpio_5 55 eecs (default) / gpio5 gpio_6 58 gpio6 gpio pin functionality control the gpio_oen register is used to configure each gpio as an input or an output. e ach gpio pin has a set of registers associated with it that are configured to determine its functionality, and any relationship it has with other gp io pins or registers. each gpio pin can be configured to output a binary signal state or a serial sequenc e of bits. each gpio pin can output a single serial bit pattern or it can be programmed to continuously loop and output the pattern until stopped. the duration of the high and low periods within the sequential bit patterns can be programmed to meet the r equirements of the application. the output can be triggered to occur at any time by the local processor writing to the cor rect register or it ca n be triggered by the local ieee p recision timing protocol clock being equal to an exact time. the local processor can interrogate any gpio pin at any time or the value of the ieee precision time protocol cl ock can be captured and recorded when the specified event occurs on any of the gpio pins. the control and output of the gpio pins can be cascaded to create complex digital output sequences and waveforms. lastly, the units can be programmed to generate an inter rupt on specific conditions. the control structure for the seven gpio pins are organized into two separate units called the trigger output u nits ( tou) and the timestamp input units (tsu) . there are twelve tous and twelve tsus which can be used with any of the gpio pins. there are 32 control bytes for each of the two units to control the functionality. the depth of control is summarized in table 14 . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 64 revision 1.0 table 14 . trigger output units and timestamp input units summary trigger output units time s tamp input units 32 by tes of parameters 32 bytes of parameters trigger patterns: negative edge, positive edge, negative pulse, positive pulse, negative period, positive period, register output shift detection: negative or positive edges n egative or positive pulses pulse width: 16? bit counter @ 8 ns each (524288 ns max imum ) two edge/one pulse (2 time stamps) detection capability (times tamp units 10:0) cycle width: 32?bit counter @ 1 ns each (4.2 9s max imum ) eight edge/four pulse (8 time stamps) detection (times tamp unit 11) cycle count: 16?bit counter (0 = infinite loop) cascadable to detect multiple edges total cascade mode cycle time: 32? bit counter @ 1 ns each shift register: 16? bits (o nly for register shift o utput mode) c ascadable to generate complex waveforms gpio pin control register layout most of the registers used to control the t imes tamp units and the trigger output u nits are duplicated for each gpio pin. there are a few registers which are associated with all the overall functionali ty of all the gpio pins or only specific gpio pins. these are summarized in table 15 . table 15 . gpio pin control register layout register name register location related to which trigger output units or timestamp units trigger error register C trig_err 0x200 C 0x201 all gpio trigger output units trigge r active register C trig_active 0x202 C 0x203 all gpio trigger output units trigger done register C trig_done 0x204 C 0x205 all gpio trigger output units trigger enable register C trig_en 0x206 C 0x207 all gpio trigger output units trigger sw reset register C trig_sw_rst 0x208 C 0x209 all gpio trigger output units trigger unit 12 output pps pulse width register ? trig12_pps_width 0x20a C 0x20b gpio trigger unit 1, 12 timestamp ready register C ts_rdy 0x400 C 0x401 all gpio timestamp input units timestamp enable register C ts_en 0x402 C 0x403 all gpio timestamp input units timestamp software reset register C ts_sw_rst 0x404 C 0x405 all gpio timestamp input units downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 65 revision 1.0 figure 12 . trigger output unit organization and associated registers downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 66 revision 1.0 figure 13 . timestamp input unit organization and associated registers downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 67 revision 1.0 gpio trigger output units and timestamp input unit interrupts the t rigger o utput u nits and the timestamp input u nits can be programmed to generate interrupts when specified events occur. the interrupt control structure is shown in figure 14 and figure 15 . figure 14 . trigger unit interrupts figure 15 . timestamp input unit interrupts downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 68 revision 1.0 using the gpio pins with the trigger output units the twelve trigger output units (tou) can be used to generate a variety of pulses, clocks , waveforms, and data streams at user selectable gpio pins. the tou will generate the user - specified output starting at a specific time with respect to the ieee 1588 precision time clock. this section provides some information on configuring the t ous to generate specific types of output. in the information below, the value x represents one of the twelve tous. since this area of the device is very flexible and powerful, please reference application note anlan203 for additional information on cr eating specific types of waveforms and utilizing this feature. when using a single tou to control multiple gpio pins, there are several detail s of functionality that must be taken into account. when switching between gpio pins, the output value on those pins can be affected. if a tou changes t he gpio pin level to a high value, writing to this unit s configuration register to change the addressed gpio pin to a different one will cause the hardware to drop the level in the previous gpio pin and set the n ew gpio pin to a high value. to prevent the second gpio pin from going high immediately, the tou must be reset prior t o programming in a different gpio pin value. creating a low?going pulse at a specific time specifying the time the desired trigger time will be set in trigx_tgt_nsh, trigx_tgt_nsl, trigx_t gt_sh, and trigx_tgt_sl registers. specifying the pulse parameters trigx_cfg_1[6:4] = 010 for negative pulse generation. trigx_cfg_2[15:0] = pulse w idth where each unit is 8 ns. associate this trigger output unit to a specific gpio pin trigx_cfg_1[3:0] = selects gpio pin to use. set -u p interrupts if needed if it is desired to get notification that the trigger output event occurred, set up the fo llowing reg isters: ? trigx_cfg_1, bit[8] (trigger notify) = 1 is one requirement for enabling interrupt on done or error. ? set the corresponding trigger unit interrupt enable bit in the ptp_trig_ie register. enabling the trigger output unit set the corresponding t r igger unit e nable bit in the trig_en register. notes : be aware that for a low - going pulse i n no n?cascaded mode (single mode), th e output will be driven by the unit to a high level when the trigger unit is enabled. in cascade mode, the output will be driven by the u nit to the high state 8 ns prior to the programmed trigger time. creating a high? going pulse at a specific time specifying the time the desired trigger time will be set in trigx_tgt_nsh, trigx_tgt_nsl, trigx_t gt_sh, and trigx_tgt_sl registers. specifying the pulse parameters trigx_cfg_1[6:4] = 011 for positive pulse generation. trigx_cfg_2[15:0] = pulse w idth where each unit is 8ns. associate this trigger output unit to a specific gpio pin trigx_cfg_1[3:0] = selects gpio pin to use. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 69 revision 1.0 set -u p interrupts if needed if it is desired to get notification that the trigger output event occurred, set up the fo llowing registers: ? trigx_cfg_1, bit[8] (trigger notify) = 1 is one requirement for enabling interrupt on done or error. ? set the corresponding trigger unit interrupt enable bit in the ptp_trig_ie register. enabling the trigger output unit set the corresponding trigger unit e nable bit in the trig_en register. notes : be aware that for a high - going pulse in non?cascaded mode (single mode), the output will be driven by the unit to a low level when the trigger unit is enabled. in cascade mode, the output will be dr iven by the unit to the low state 8ns prior to the programmed trigger t ime. creating a free running clock source specifying the time typically there is no need to set up a desired trigger time with respect to a free running clock. ther e are two ways that the fre e running clock can be started: ? set up a desired trigger time in the trigx_tgt_nsh, trigx_tgt_nsl, trigx_tg t_sh, and trigx_tgt_sl registers. ? after parameters have been set up, start the clock by setting the trigger -n ow bit, bit[8], in the trigx_cfg_1 register. specifying the clock parameters trigx_cfg_1[6:4] = 101 for generating a positive periodic signal. high part of cycle defined by bits[15:0] in the trigx_c fg _2 register. each unit is 8ns. cycle width defined by bits[15:0] in trigx_cfg_3 and trigx_cfg_4 registers. each un it is 1ns. continuous clock by setting trigx_cfg_5, bits[15:0] = 0. associate this trigger output unit to a specific gpio pin trigx_cfg_1[3:0] = selects gpio pin to use. set -u p interrupts if needed if it is desired to get notification that the trigger output event occurred, set up the fo llowing registers: ? trigx_cfg_1, bit[8] (trigger notify) = 1 is one requirement for enabling interrupt on done or error. ? set the corresponding trigger unit interrupt e nable bi t in the ptp_trig_ie register. enabling the trigger output unit set the corresponding trigger unit e nable bit in the trig_en register. note : because the frequencies to be generated are based on the period of the 125mhz clock, there are some limitations that the user must be aware of. certain frequencies can be created with unvary ing duty cycles. however, other frequencies may incur some variation in duty cycle. there are methods of utilizing the trigger unit 2 clock edge o utput select bit (bit[7] in of reg. 0x248 C 0x249) and gpio1 to control and minimize the variances. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 70 revision 1.0 creating finite lengt h periodic bit streams at a specific time this example implies that a uniform clock will be generated for a specific number of clock cy cles. specifying the time the desired trigger time will be set in trigx_tgt_nsh, trigx_tgt_nsl, trigx_t gt_sh, and trigx_tgt_sl registers. specifying the finite length periodic bit stream parameters trigx_cfg_1[6:4] = 101 for generating a positive periodic signal. high part of cycle defined by bits[15:0] in the trigx_c fg _2 register. each unit is 8ns. cycle width def ined by bits[15:0] in trigx_cfg_3 and trigx_cfg_4 registers. each unit is 1 ns. finite length count established by setting trigx_cfg_5, bits[15:0] = number of c ycles. each unit is one cycle. associate this trigger output unit to a specific gpio pin trigx_cfg_1[3 :0] = selects gpio pin to use. set -u p interrupts if needed if it is desired to get notification that the trigger output event occurred, set up the fo llowing registers: ? trigx_cfg_1, bit[8] (trigger notify) = 1 is one requirement for enabling interrupt on done o r error. ? set the corresponding trigger unit interrupt e nable bi t in the ptp_trig_ie register. enabling the trigger output unit set the corresponding trigger unit e nable bit in the trig_en register. creating finite length non?uniform bit streams at a specific time generation of a finite length non?uniform waveform which is a multiple of the bit pattern stored in the data storage register. specifying the time the desired trigger time will be set in trigx_tgt_nsh, trigx_tgt_nsl, trigx_t gt_sh, and trigx_tgt_sl registers. specifying the finite length non?uniform bit st ream parameters trigx_cfg_1[6:4] = 110 for generating signal based on contents of data register. 16 - bit pattern stored in trigx_cfg_6 register. bit width defined by bits[15:0] in trigx_cfg_3 and trigx_cfg_4 registers. each unit is 1ns. bit length of finite pattern is established by shifting the data register n times . set trigx_cfg_5, bits[15:0] = n. associate this trigger output unit to a specific gpio pin trigx_cfg_1[3 :0] = selects gpio pin to use. set -u p interrupts if needed if it is desired to get notification that the trigger output event occurred, set up the fo llowing registers: ? trigx_cfg_1, bit[8] (trigger notify) = 1 is one requirement for enabling interrupt on done or error. ? set the corresponding trigger unit interrupt enable bit in the ptp_trig_ie register . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 71 revision 1.0 enabling the trigger output unit set the corresponding trigger unit e nab le bit in the trig_en register. creating complex waveforms at a specific time complex waveforms can be created by combining the various functions available in the trigger output units using a method called cascading. figure 16 illustrates the generation of a complex waveform onto one gpio pin. trigger output unit 1 (tou1) and trigger output unit 2 (tou2) are cascaded to produce the complex waveform. cascading allo ws multiple outputs to be sequentially output onto one gpio pin. in figure 17 , the waveform created by tou1 is output first on the selected gpio pin when the indicated tou1 trigger time is reached. the value in trig 1_cfg7 and trig1_cfg 8 will be added to the tou1 trigger time and the next tou1 output will occur at that time. meanwhi le, tou2 will operate in the same manner; outputting its waveform at tou2 trigger time and then outputting again at a tim e trig2_cfg7 and trig2_cfg 8 later. the trigx_cfg7 & 8 register values must be the same for all tous that are c ascaded together. the number of times tou1 and tou2 will be output will depend on the cycle times programmed into the trig1_cfg6 and tri g2_cfg6 registers. care must be taken to select the correct values so as to avoid erroneous overlap. additional steps are required in setting up cascaded tous: ? specifying which tou in the c ascade is the last unit called the tail unit. ? the last tou in a cascade setup should ha ve its tail bit set to 1. figure 16 . complex waveform generation using cascade mode downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 72 revision 1.0 using the gpio pins with the timestamp input units the 12 timestamp input units (tsu) can be set up to capture a variety of inputs at user selectable gpio pi ns. the current time of the precision time clock time will be captured and stored at t he time in which the input event occurs. this section provides some information on configuring the timestamp input units. in the information below, the value x represents one of the twelve timestamp input units. since this area of the device is very fl exible and powerful, it is advised that you contact your micrel representative for additional information on capturing specific types of wavef orms and utilizing t his feature. timestamp value each timestamp input unit can capture two sampled values of timestamps. these first two values r emain until read, even if more events occur. the timestamp value captured consists of three parts which are lat ched in three regist ers: ? sample #1, the seconds value; tsx_smpl1_sh, tsx_smpl1_sl ? sample #1, the nanoseconds value; tsx_smpl1_nsh, tsx_smpl1_nsl ? sample #1, the sub - nanoseconds value; tsx_smpl1_sub_ns ? sample #2, the seconds value; tsx_smpl2_sh, tsx_smpl2_sl ? sample #2, the nanoseconds value; tsx_smpl2_nsh, tsx_smpl2_nsl ? sample #2, the sub - nanoseconds value; tsx_smpl2_sub_ns the actual value in tsx_smpl1/2_sub_ns is a binary value of 0 thru 4 which i ndicates 0ns, 8ns, 16ns, 24ns, or 32ns. note that the processor needs to add this value to the seconds and nanoseconds value to get the closest true value of t he timestamp event. number of timestamps available each timestamp input unit can capture two events or two timestamps values. note that the exception t o this is tsu12. tsu12 can capture eight events and thus has eight sample time registers (smpl1 thru smpl8) allowing for more robust timing acquisition in one tsu. note that the amount of samples for any gi ven gpio pin can be increased by cascading time stamp unit. when tsus are cascaded, the incoming events are routed to a sequentially established order of tsus for capture. for example, you can cascade tsu12, and tsu 1?4 to be able to capt ure 12 timestamps off of one gpio pin. cascading is set up in the tsx_cfg registers. even ts that can be captured the timestamp input units can capture rising edges and falling edges. in this case, the timestamp of the event will be captured in the sample #1 timestamp registers. a pulse can be captured if rising edge detection is combined with falling edge detection. in this case, one edge will be captured in the sample #1 timestamp registers and the other edge will be captured in the sample #2 timestamp registers. this functionality is programmed in the tsx _cfg register for each timestamp unit. timestamping a n incoming low ? g oing edge specifying the edge parameters tsx_cfg bit[6] = 1 associate this time s tamp unit to a specific gpio pin tsx_cfg bits [11:8] = selected gpio pin # set - up interrupts if needed set the corresponding timestamp input unit interrupt enable bit in the ptp_ts_ie register. enabling the times tamp input unit set the corresponding timestamp input unit enable bit in the ts_en register. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 73 revision 1.0 timestamping an incoming high?going edge specifying the edge parameters ts x_cfg bit[7] = 1 associate this times tamp input unit to a specific gpio pin tsx_cfg bits [11:8] = selected gpio pin # set -u p interrupts if needed set the corresponding t imestamp input u nit i nterrupt e nable bit in the ptp_ts_ie register. enabling the times tamp input unit set the corresponding timestamp input unit e nable bit in the ts_en register. timestamping a n incoming low ? going pulse or high - going pulse specifying the edge parameters tsx_cfg bit[7] = 1 ts x_cfg bit[6] = 1 associate this timestamp input unit to a specific gpio pin tsx_cfg bi ts 11:8] = selected gpio pin # set - up interrupts if needed set the corresponding t imestamp input u nit i nterrupt enable bit in the ptp_ts_ie register. enabling the timestamp input unit set the corresponding timestamp input unit e nable bit in the ts_en register. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 74 revision 1.0 device clocks a 25mhz crystal or oscillator clock is required to operate the device. this clock is used as input to a pll clock synthesizer which generates 125mhz, 62.5mhz , and 31.25mhz clocks for the ksz8462 system tim ing. table 16 summarizes the clocking. table 16 . ksz8462 device clocks clock usage source strapping option 25 mhz used for general system internal clocking. u sed to generate an internal 125 mhz clock for the ieee 1588 block. a 25 mhz crystal connected between pins x1 and x2. (or) a 25 mhz oscillator that is connected to only the x1 pin. the x2 pin is left unconnected. none seep rom clock used to clock data to or from the serial eeprom. 2.5mhz, divided down from the 25 mhz input clock. can also be software generated via register 0x122 C 0x123 (eepcr). after reset time, this is the only way to generate the clock to the serial eeprom for access. note that the clock tree power - down control register (0x038 C 0x039) ctpdc is used to power - down the clocks in various areas of the device. there are no other internal register bits which control the clock generatio n or usage in the device. gpio and ieee 1588 related clocking the gpio and ieee 1588 - related circuits both utilize the 25mhz clock and the derived 125mhz clock. the tolerance and accuracy of the 25mhz clock source will affect the ieee 1588 jitter and offset in a sys tem utilizing multiple slave devices. therefore, the 25mhz source should be chosen with care towards the performance of the application in mind. using an oscillator will generally provide better results. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 75 revision 1.0 power the ksz8462 device requires a single 3.3v supply to operate. an internal low v oltage ldo provides the necessary low voltage (nominal ~1.3v) to power the analog and digital logic cores. the various i/os can be operated at 1. 8v, 2.5v, and 3.3v. table 17 illustrates the various voltage options and requirements of the device. table 17 . voltage options and requirements power signal name device pin requirement vdd_a3.3 9 3.3v input power to the analog blocks in the device. vdd_io 21, 30, 56 choice of 1.8v or 2.5v or 3.3v for the i/o circuits. these input power pins power the i/o circuitry of the device. this voltage is also used as the input to the internal low -v oltage regulator. vdd_al 6 filtered low -v oltage analog input voltage. this is where filtered low v oltage is fed back into the device to power the a nalog block. vdd_col 16 filtered low -v oltage ad input voltage. this pin feeds low v oltage to digital circuits within the analog block. vdd_l 40, 51 output of internal low v oltage ldo regulator. this voltage is available on these pins to allow connection to external capacitors and ferrite beads for filtering and power integrity. these pins must be externally connected to pins 6 and 16. if the internal ldo regulator is turned off, these pins become power inputs. . agnd 3, 8, 12 analog ground . dgnd 20, 29, 39, 50, 57 digital ground . the preferred method of configuring the l ow -v oltage related power pins when using an external low - voltage regulator is illustrated in figure 17 . the number of capacitors, values of capacitors, and exact placement of component s will depend on the specific design. figure 17 . recommended low - voltage power connection using an external low - voltage - regulator downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 76 revision 1.0 internal low voltage ldo regulator the ksz8462 reduces board cost and simplifies board layout by integrating a low - noise internal low -v oltage ldo regulator to supply the nominal ~1.3v core power voltage for a single 3.3v power supply solution. if it i s desired to take advantage of an external low -v oltage supply that is available, the internal low -v oltage regulator can be disabled to save power. the ldo_off bit, bit [7] in register 0x748 is used to enable or disable the interna l low -v oltage regulator. the default state of the ldo_off bit is 0 which enables the internal low -v oltage regulator. turning off the internal lo w-v oltage regulator will require software to write a 1 to that control bit. during the time from power up to setting this bit, both t he external voltage supply and the internal regulator will be supplying power. note that it is not n ecessary to turn off the internal low -v oltage regulator. no damage will occur if it is left on. however, leaving it on will result in less than optimized power consumption. the internal regulator takes its power from vdd_io, and functions best when vdd_io is 3.3v or 2.5v. if vdd_io is 1.8v, the output voltage will be decreased somewhat. for optimal performance, an external power s upply, in place of the internal regulator, is recommended when vdd_io is 1.8v. the preferred method of configuring the low -v oltage related power pins for using the internal low -v oltage regulator is illustrated in figure 18 . the output of the internal regulator is available on pins 40 and 51 and is f iltered using external capacitors and a ferrite bead to supply power to pins 6 and 16. the number of capacitors, values of capacitors, and exact placement of components will depend on the specific design. figure 18 . recommended low - voltage power connections using the internal low - voltage regulator downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 77 revision 1.0 power management the ksz8462 supports enhanced power management features in low power state with energy detection t o ensure low?power dissipation during device idle per iods. there are three operation modes under the power management function which is controlled by two bits in the power management control and w ake? up event status register (pmctrl, 0x032 C 0x033) as shown below: ? pmctrl[1:0] = 00 normal operation mode ? pmc trl[1:0] = 01 energy detect mode ? pmctr l[1:0] = 10 global soft power - down mode table 18 indicates all internal function blocks status under three different power management operation modes . table 18 . power management and internal blocks ksz8462 function blocks power management operation modes normal mode energy detect mode soft power - down mode internal pll clock enabled enabled disabled tx/rx phys enabled energy detect at rx disabled macs enabled disabled disabled host interface enabled enabled disabled normal operation mode normal operation m ode is the power management mode entered into after device power?up or after hardware reset pin 63. it is established via bits[1:0] = 00 in the pmctrl register. when t he ksz8462 is in normal operation mode, all pll clocks are running, phys and macs are on, and the cpu is ready to read or write the ksz846 2 through host interface. during the normal operation mode, the host cpu can change the power management mode bits[1:0] in the pmctrl register to transition to another desired power management mode energy detect mode energy detect mode provides a mechanism to save more power than in normal operation mode when the ksz8462 is not connected to an active link partner. for example, if the cable is not present or it is connected to a powered - down partner, the ks z8462 can automatically enter the low power state in energy detect mode. once activity res umes after attaching a cable or by a link partner attempting to establish a link, the ksz8462 will automatically power up into the normal power state in energy detect normal power state. the energy detect mode function is not valid in fiber mode using the ksz8462fhl. energy detect mode consists of two states, normal power state and low power state. whi le in low - power state, the ksz8462 reduces power consumption by disabling all circuitry except the energy det ect circuitry of the receiver. energy detect mode is enabled by setting bits[1:0] = 01 in the pmctrl register. when the ksz8462 is in this mode, it will monitor the cable energy. if there is no energy on the cable for a time longer than a pre?configured value determined by bits[7:0] (go?sleep t ime) in the gst register, the device will go into the low power state. when the ksz8462 is in low power state, it will keep monitoring the cable energy. once energy is detected from the cable and is present for a time longer than 100ns, the ksz8462 will enter the normal power state. the ksz8462 will assert the pme output pin if the corresponding enable bit[0] is set in the pme e register (0x034) or generate an interrupt to signal that an energy detect event has occurred if the corresponding enable bit[2] is set in the ier register (0x190). once the local power management unit detects the pme output is asserted or that the inter rupt is active, it will power up the host processor and issue a wake - up command which is a read cycle to read the globe reset register, grr (0x126) to wake up the ksz8462 from the low power state to the normal power state. when the ksz8462 device is in the normal power state, it is able to transmit or receive packet from the cable. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 78 revision 1.0 global soft power - down mode soft power - down mode is entered by setting bits[1:0] = 10 in pmctrl register. when the device is in t his mode, all pll clocks are disabled, the phys and the macs are off, all internal regi sters value will change to their default value (except the biu, qmu registers), and the host interface is only used to wake?up this device from t he current soft power - down mode to normal operation mode by setting bits[1:0] = 00 in the pmctrl register. note that the registers within the qmu block will not be changed to their d efault values when a soft power - down is issued. all strap?in pins are sampled to latch any new values when soft power -d own is disabled. energy - efficient ethernet (eee) energy - efficient e thernet (eee) is implemented in the ksz8462 as described in the ieee 802.3az specification for mii operations on port 1 and port 2. the eee function is not available for fiber m ode ports using the ksz8462fhl. eee is not perfo rmed at port 3 since that is a paralle l h ost interface. the mii connection s between the mac and phy blocks are internal to the chip and are not visible to the user. the standards are defined around a mac that supports speci al signaling associated with eee. eee saves power by keeping the voltage on the ethernet cab le at approximately 0v for as often as possible during periods of no traffic acti vity. this is called low - power i dle state (lpi). however, the link will respond automatically when traffic resumes and do so in such a way as to not cause blocking or dropping of any packets (t he wake - up time for 100bt is specified to be less than 30s). the transmit and receive directions are independently controlled. note the eee is not specified or implemented for 10bt. in 10bt, the transmitter i s already off during idle periods. the eee feature is enabled by default. eee is auto - negotiated independently for each direction on a link, and is enabled only if both nodes on a link support it. to disable eee, clear the next page e nable bit(s) for the desired port(s) in the pcseeec register (0x0f3) and restart auto - negotiation. based on the eee specification, the energy savings from eee occur s at the phy level. however, the ksz8462 reduces the power consumption not only in the phy block but also in the mac and switch blocks by shutting down any unused clocks as much as possible when the device is at low - power i dle state. a comprehensive lpi request on/off policy is also built?in at the switch level to determine when to issue lpi requests and when t o stop th e lpi request. some software control options are provided in the device to terminate the lpi request in t he early phase when certain events occur to reduce the latency impact during lpi recovery. a configurable lpi recovery time register is provided at each port to specify the recovery time (25s at default) required for the ksz8462 and its link partner before they are ready to transmit and receive a packet after going back to the normal state. for details, refer to the ksz8462 eee registers (0x0e0 C 0x0f7) description. figure 19 illustrates the time during which lpi mode is active is during what is called quie t time. figure 19 . traffic activity and eee downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 79 revision 1.0 transmit direction control for mii mode for ports 1 and 2, l ow - power idle (lpi) state for the transmit direction will be entered when the internal eee mac signals to its phy to do so. the phy will stay in the t ransmit lpi stat e as long as indicated by the mac . t he tx_clk is not stopped. even though the phy is in lpi state, it will periodically leave the lpi state to tr ansmit a refresh signal using specific transmit code bits. this allows the link partner to keep track of the long term variation of channel char acteristics and clock drift between the two partners. approximately every 20 ? 22 milliseconds, the phy will transmit a bit pattern to its link partner of duration 200 ? 220 microseconds. the refresh times are shown in . receive direction control for mii mode if enabled for lpi mode, upon receiving a p code bit pattern (refresh), the phy will enter the lpi state and signal to the internal mac . if the phy receives some non?p code bit pattern, it will signal to the mac to return to normal frame mode . the phy can turn off the rx_clk after 9 or more clocks have occurred in the lpi state. in the eee - compliant environment, the internal phys will be monitoring and expecting the p code (refresh) bit pattern from its link partner that is generated approximately every 20 ? 22 milliseconds, with duration of about 200 ? 220 microseconds. this allows the link partner to keep track of the long term variation of channel characteris tics and clock drift between the two partners. registers associated with eee the following registers are used to configure or manage the eee feature. ? reg. dch, ddh ? p1anpt C port 1 auto?negotiation next page transmit register ? reg. deh, dfh ? p1alprnp C port 1 auto?negotiation link partner received next page register ? reg. e0h, e1h ? p1eeea C port 1 eee and link partner advertisement register ? reg. e2h, e3h ? p1eeewec C port 1 eee wake error count reg ister ? reg. e4h, e5h ? p1eeecs C port 1 eee control/status and auto?negotiation expansion register ? reg. e6h ? p1lpirtc C port 1 lpi recovery time counter register ? reg. e7h ? bl2lpic1 C buffer load to lpi control 1 register ? reg. e8h, e9h ? p2anpt C port 2 auto?negotiation next page transmit register ? reg. eah, ebh ? p2alprnp C port 2 auto?negotiation link partner received next page register ? reg. ech, edh ? p2eeea C port 2 eee and link partner advertisement register ? reg. eeh, efh ? p2eeewec C port 2 eee wake error count register ? reg. f0h, f1h ? p2eeecs C port 2 eee control/status and auto?negotiation expansion register ? reg. f2h ? p2lpirtc C port 2 lpi recovery time counter register ? reg. f3h ? pcseeec C pcs eee control registe r ? reg. f4h, f5h ? etlwtc C empty txq to lpi wait time control register ? reg. f6h, f7h ? bl2lpic2 C buffer load to lpi control 2 register downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 80 revision 1.0 wake - on - lan wake - on - lan is considered a power - management feature in that it can be used to communicate to a specific network device and tell it to wake up from sleep mode and be prepared to transfer data. the ksz8462 can be programmed to notify the host of the wake - up detected condition. it does so by assertion of the interrupt signal pin (intrn) or the power management event signal pin (pme). a wake?up event is a request for hardwar e and/or software external to the network device to put the system into a powered state (working). there are four events t hat will trigger the wake - up interrupt to occur. they are: 1. detection of an energy signal over a pre?configured value (indicated by bit [2] in the isr register being set) 2. detection of a linkup in the network link state (indicated by bit[3] in the isr regi ster being set) 3. receipt of a magic packet (indicated by bit[4] in the isr register being set) 4. receipt of a network wake?up frame (indicated by bit[5] in the isr register being set) there are also other types of wake?up events that are not listed here as m anufacturers may choose to implement these in their own way. detection of energy the energy is detected from the cable and is continuously presented for a time longer t han pre?configured value, especially when this energy change may impact the level at whi ch the system should re?enter to the normal power state. detection of linkup link status wake events are useful to indicate a linkup in the networks connectivity status. wake?up packet wake? u p packets are certain types of packets with specific crc values that a syst em recognizes as a wake - up frame. the ksz8462 supports up to four user defined wake?up frames shown below: ? wake? u p frame 0 is defined in wake - up frame registers (0x130 C 0x13b) and is enabled by bit [0] in the wake - up frame register (0x12a). ? w ake?up frame 1 is defined in wake?up frame registers (0x140 C 0x14b) and is enabled by bit [1] in the wake - up frame register (0x12a). ? wake?up frame 2 is defined in wake?up frame registers (0x150 C 0x15b) and is enabled by bit [2] in the wake - up frame regis ter (0x12a). ? wake?up frame 3 is defined in wake?up frame registers (0x160 C 0x16b) and is enabled by bit [3] in the wake - up frame register (0x12a). magic packet? magic packet (mp) technology is used to remotely wake up a sleeping or powered off pc on a la n. this is accomplished by sending a specific packet of information, called a mp frame, to a node on the network. when a pc capable of receiving the specific frame goes to sleep, it enables the mp rx mode in the lan controller, and when the lan controller receives a mp frame, the lan controller will alert the system to wake up. mp is a standard feature integrated into the ksz8462 . the controller implements multiple advanced power?down modes including mp to conserve power and operate more efficiently. once t he ksz8462 has been put into mp enable mode (wfcr[7] = 1), it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the controller this is a mp frame. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 81 revision 1.0 the specific sequence consists of 16 duplications of the ieee address of this node, with no breaks or interruptions. this sequence can be located anywhere within the packet, but must be preceded by a sync hronization stream. the synchronization stream allows the scanning state machine to be much simpler. the synchronization stream is defined as 6 bytes of ffh. the device will also accept a broadcast frame, as long as the 16 duplications of the ieee address match the address of the machine to be awakened. example: if the ieee address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the lan controller would be scanning for the data sequence (assuming an ethernet frame): destination source C misc ? ff ff ff ff ff ff ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ?11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? 11 22 33 44 55 66 ? misc ? crc. there are no further restrictions on an mp frame. for example, the sequence could be in a tcp/ip packet or an ipx packet. the frame may be bridged or routed across the network without aff ecting its ability to wake?up a node at the frames destination. if the lan controller scans a frame and does not find the specific sequence shown above, it discards the fr ame and takes no further action. if the ksz8462 controller detects the data sequence, however, it then alerts the pcs pow er management circuitry (assert the pme pin) to wake up the system. interrupt generation on power management related events there are two ways an interrupt can be generated to the host whenever a power management related even t takes place. the resulting interrupts are via the pme signal pin or via the intrn signal pin. the usage is described in the following sub - sections: to generate an interrupt on the pme signal p in the pmee register (0x034 C 0x035) contains the bits needed to control generating an interrupt on the pme signal pin whenever specific power management related events occur. the power management events controlled by this register includes detection of a wake - up frame , detection of a mp , detection that the link has changed state, and detection of energy on the ethernet lines. to generate an interrupt on the intrn signal p in the ier register (0x190 C 0x191) contains the bits needed to control generating an interrupt on the i ntrn signal pin whenever specific power management related events occur. the power management events controlled by this register includes detection of a wake?up from a link state change and wake?up from detection of energy on the ethernet lines. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 82 revision 1.0 interfaces the ksz8462 device incorporates a number of interfaces to enable it to be designed into a standard network env ironment as well as a vendor unique environment. the available interfaces and details of each usage are provided in table 19 : table 19 . available interfaces interface type usage registers accessed host bus configuration and data flow provides a path for network data to be transferred to and from the host processor. provides in - band communication between a host processor and the ksz8462 device for configuration, control, and monitoring. all serial eeprom configuration and register access device can access the serial eeprom to load the mac address at power - up. in addition, the remainder of eeprom space can be written or read and used as needed by the host. 110h ? 115h phy data flow interface to the two internal phy devices. n/a bus interface unit (biu) / host interface the biu manages the host interface which is a generic indirect data bus interf ace, and is designed to communicate with embedded processors. typically, no glue logic is required when interfacing to st andard asynchronous buses and processors. supported transfers the biu can support asynchronous transfers in sram?like slave mode. to sup port the data transfers, the biu provides a group of signals as shown in table 20 . these signals are sd[15:0], cmd, csn, rdn, wrn, and intrn. note that it is intended that the csn signal be driven by logic within the host processor or by some ext ernal logic which decode the base address so the ksz8462 device does not have to do address range decoding. physical data bus size the biu supports an 8?bit or 16?bit host standard data bus. depending on t he size of the physical data bus, the ksz8462 can support 8?bit or 16?bit data transfers. for a 16?bit data bus mode, the ksz8462 allows an 8?bit and 16?bit data transf er. for an 8?bit data bus mode, the ksz8462 only allows an 8?bit data transf er. the ksz8462 supports internal data byte?swapping. this means that the system/host data bus hd[7:0] con nects to sd[7:0] for an 8?bit data bus interface. for a 16?bit data bus, the syst em/host data bus hd[15:8] and hd[7:0] connects to sd[15:8] and sd[7:0] respectively. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 83 revision 1.0 table 20 . bus interface unit signal grouping signal type function sd[15:0] i/o shared data bus 16?bit mode & cmd = 0 sd[15:0] = d[15:0] data 16?bit mode & cmd = 1: sd[10:2] = a[10:2] address sd[15:12] = be[3:0] byte enable sd[1:0] and sd[11] are not used 8?bit mode & cmd = 0 sd[7:0] = d[7:0] data 8?bit mode & cmd = 1 sd[7:0] = a[7:0] = 1st address access sd[2:0] = a[10:8] = 2nd address access sd[7:3] = not used during 2nd address access cmd input command type this command input determines the sd[15:0] shared data bus access cycle information. 0: data access 1: command access for address and byte enable csn input chip select chip select is an active low signal used to enable the shared data bus access. intrn output interrupt this low active signal is asserted low when an interrupt is being requested. rdn input asynchronous read this low active signal is asserted low during a read cycle. a 4.7k pull - up resistor is recommended on this signal. wrn input asynchronous write this low active signal is asserted low during a write cycle. little and big endi an support the ksz8462 supports either little?endian or big?endian processors. the external strap pin 62 (p2led0) is used to select between the two modes. the ksz8 46 2 host interface operates in little endian mode if this pin is pulled up during reset, or in big endian mode if this pin is pulled down during reset. if there is no external load on pin 62 duri ng reset, it will be pulled up by its internal pull - up resistor, placing the interface into little endian mode. bit [11] (endian mode selection) in rxfdpr register can be used to program ei ther little endian mode (bit [11] = 0) or big endian mode (bit [11] = 1). changes to this register bit will over - ride the pin 62 strap - in selection. software in the host processor must take care to avoid unintentionally changing bit [11] when writing to regi ster rxfdpr. asynchronous interface for asynchronous transfers, the asynchronous interface uses rdn (read) or wrn (write) signal strobe for data latching. the host utilizes the rising edge of rdn to latch read data and the ksz8462 will use the falling edge of wrn to latch write data. all asynchronous transfers are either single?data or burst?data transfers. byte or word data bus access (transfers) is supported. the biu, however, provides flexible asynchronous interfacing to communicate with various applications and architectures. no additional address latch is required. the biu qualifies both chip select ( csn ) pin and write enable ( wrn ) pin to write the address a[10:2] and be[3:0] value (in 16?bit mode) or addres s a[10:0] value (in 8?bit mode with downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 84 revision 1.0 two write accesses) into ksz8462 when cmd (command type) pin is high. the b iu qualifies the csn pin as well as the read enable (rdn ) or write enable (wrn ) pin to read or write the sd[15:0] (16?bit mode) or sd[7:0] (8?bi t mode) data value from or to ksz8462 when command type (cmd ) pin is low. in order for software to read back the previous cmd register write value when cmd is 1, the biu qualifies both the csn pin and the rdn pin to read the address a[10:2] and be[3:0] v alue (in 16?bit mode) back from the ksz8462 when cmd pin is high. reading back the addresses in 8?bit mode is not a valid operation . biu summary figure 20 shows the connection for different data bus sizes. all of control and status registers in the ksz8462 are accessed indirectly depending on cmd pin. the command sequence to access the specified control or status register is to write the registers addr ess (when cmd = 1) then read or write this register data (when cmd = 0). if both rdn and wrn signal s in the system are only used for ksz8462, the csn pin can be forced to active low to simplify the system design. the c md pin can be connected to host address line ha[0] for 8?bit bus mode or ha[1] for 16?bit bus mode. figure 20 . ksz8462 8- bit and 16 - bit data bus connections example: assume that the register space is located at an external i/o base address of 0x0300, a 16 - bit data path is used, and it is desired to read two bytes of data from address 0xd0: ? external address decoding should decode the 0x0300 base address and create a signal for the csn pin . ? the host address line 1 (ha[1]) is connected to the cmd input pin. for a h ost write to the device, the ha[1] being asserted will make cmd = 1 which will indicate that the data on the ds[15:0] bus are ad dress and byte enable bits. ? as shown in figure 23 , the address bits a[10:2] are on sd[10:2]. ? write a value of 0x30d0 (r egist er offset of 0xd0 with be[1:0] (set on the sd[16:0] bus) to address 0x0302. (this sets up the address for the upcoming read operation by writing the desired destination address to be read. ) ? read the value from address 0x0300 with ha[1] = 0 (cmd = 0). the csn pin is driven a gain by the decode of the base address of 0x0300. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 85 revision 1.0 serial eeprom interface a s erial eeprom i nterface has been incorporated into the device to enable loading the mac address into the devic e at power - up time with a value from an externa l s erial eeprom. this feature is turned on using a strapping option on pin 46. at power - up time, the voltage on pin 46 is sampled. if the voltage is found to be high, t he first seven words of the s erial eeprom will be read. registers 0x110 C 0x115 will be loaded with words 01h C 03h. a pull - up resistor is connected to pin 46 to create a high state at power - up time (see strapping options ). after the de?assertion of rstn, the ksz8462 reads in the seven words of data. note that a 3?wire 1kbit s erial eeprom utilizing 7?bit addresses must be used. other size options will not function correctly . a 93c46 or equivalent type device meets these requirements. the eeprom must be organized in 16?bit mode. the serial eeprom interface signals are muxed with three of the gpio signals on pins 53, 54, and 55. register 0x0d6 C 0x0d7 bits[1, 2, 5] are used to select between the serial eeprom function or the gpio funct ion. the default state of that register at power up is to configure the pins for s erial eeprom usage. if the eedio pin (pin 54) is pulled high, then the ksz8462 performs an automatic read of words 0h ? 6h in the external eeprom after the de? assertion of r eset. the eeprom values are placed in certain host?accessible registers. eepr om read/write functions can also be performed by software read/writes to the eepcr (0x122) regi sters. see figure 25 in the timing specification section for the details of the serial eeprom access timing. a sample of the ksz8462 eeprom format is shown in table 21 . table 21 . ksz8462 serial eeprom format word 15 8 7 0 0h reserved 1h host mac address byte 2 host mac address byte 1 2h host mac address byte 4 host mac address byte 3 3h host mac address byte 6 host mac address byte 5 4h C 6h reserved 7h ? 3fh not used for the ksz8462 (available for user defined purposes) downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 86 revision 1.0 device registers the ksz8462 device has a rich set of registers available to manage the functionality of the devi ce. access to these registers is via the host interface (biu) . the device can be programmed to au tomatically load register locations 0x110 C 0x115 with a mac address stored in word locations 01h C 03h in an external s erial eeprom. figure 21 provide s a global picture of accessibility via the various interfaces and addressing ranges from the perspect ive of each interface. figure 21 . interface and register mapping the registers within the linear 0x000 C 0x7ff address space are all accessible via the host interface bus by a microprocessor or cpu. the mapping of the various functions within that linear address space i s summarized in table 22 . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 87 revision 1.0 table 22 . mapping of functional areas within the address space register locations device area description 0x000 C 0x0ff switch control and configuration registers which control the overall functionality of the switch, mac, and phys 0x026 C 0x031 indirect access registers registers used to indirectly address and access four distinct areas within the device. ? mib (management information base) counters ? static mac address table ? dynamic mac address table ? vlan table 0x044 C 0x06b phy1 and phy2 registers the same phy registers as specified in ieee 802.3 specification 0x100 C 0x16f interrupts, global reset, biu r egisters and bits associated with interrupts, global reset, and the biu 0x170 C 0x1ff qmu r egisters and bits associated with the qmu 0x200 C 0x5ff ieee 1588 ptp event trigger control and output registers r egisters used to configure and use the ieee 1588 trigger functions 0x600 C 0x7ff ieee 1588 pt p clock and global control r egisters which control the ieee ptp clock control, port egress, messaging, port ingress/egress timestamp attributes downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 88 revision 1.0 register map of cpu accessible i/o registers the registers in the address range 00h through 7ffh can be read or written by a local cpu attached to the h ost interface. i f enabled, registers 0x110 C 0x115 can be loaded at power on time by contents in the serial eeprom. these regis ters are used for configuring the mac address of the device. i/o registers the f ollowing i/o register space mapping table applies to 8?bit or 16?bit locati ons. depending upon the mode selected, each i/o access can be performed using 8?bit or 16?bit wide transfers. internal i/o register space mapping for switch control and co nfiguratio n (0x000 C 0x0ff) i/o register offset location re gister name default value description 16 ? bit 8 ? bit 0x000 C 0x001 0x000 0x001 cider 0x8433 chip id and enable register [15:0] 0x002 C 0x003 0x002 0x003 sgcr1 0x3450 switch global control register 1 [15:0] 0x004 C 0x005 0x004 0x005 sgcr2 0x00f0 switch global control register 2 [15:0] 0x006 C 0x007 0x006 0x007 sgcr3 0x6320 switch global control register 3 [15:0] 0x008 C 0x00b 0x008 0x00b reserved (4- bytes) dont care none 0x00c C 0x00d 0x00c 0x00d sgcr6 0xfa50 switch global control register 6 [15:0] 0x00e C 0x00f 0x00e 0x00f sgcr7 0x0827 switch global control register 7 [15:0] 0x010 C 0x011 0x010 0x011 macar1 0x0010 mac address register 1 [15:0] 0x012 C 0x013 0x012 0x013 macar2 0xa1ff mac address register 2 [15:0] 0x014 C 0x015 0x014 0x015 macar3 0xffff mac address register 3 [15:0] 0x016 - ? 0x017 0x016 0x017 tosr1 0x0000 tos priority control register 1 [15:0] 0x018 ? 0x019 0x018 0x019 tosr2 0x0000 tos priority control register 2 [15:0] 0x01a ? 0x01b 0x01a 0x01b tosr3 0x0000 tos priority control register 3 [15:0] 0x01c ? 0x01d 0x01c 0x01d tosr4 0x0000 tos priority control register 4 [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 89 revision 1.0 internal i/o register space mapping for switch control and co nfiguration (0x000 C 0x0ff) (continued) i/o register offset location re gister name default value description 16 ? bit 8 ? bit 0x01e ? 0x01f 0x01e 0x01f tosr5 0x0000 tos priority control register 5 [15:0] 0x020 ? 0x021 0x020 0x021 tosr6 0x0000 tos priority control register 6 [15:0] 0x022 ? 0x023 0x022 0x023 tosr7 0x0000 tos priority control register 7 [15:0] 0x0 24 ? 0x0 25 0x0 24 0x0 25 tosr8 0x0000 tos priority control register 8 [15:0] 0x0 26 ? 0x0 27 0x0 26 0x0 27 iadr1 0x0000 indirect access data register 1 [15:0] 0x0 28 ? 0x0 29 0x0 28 0x0 29 iadr2 0x0000 indirect access data register 2 [15:0] 0x0 2a ? 0x0 2b 0x0 2a 0x0 2b iadr3 0x0000 indirect access data register 3 [15:0] 0x0 2c ? 0x0 2d 0x0 2c 0x0 2d iadr4 0x0000 indirect access data register 4 [15:0] 0x0 2e ? 0x0 2f 0x0 2e 0x0 2f iadr5 0x0000 indirect access data register 5 [15:0] 0x0 30 ? 0x0 31 0x0 30 0x0 31 iacr 0x0000 indirect access control register [15:0] 0x0 32 ? 0x0 33 0x0 32 0x0 33 pm ctrl 0x0000 power manageme nt control and wake?up event status register [15:0] 0x0 34 ? 0x0 35 0x0 34 0x0 35 pm ee 0x0000 power manageme nt event enable register [15:0] 0x0 36 ? 0x0 37 0x0 36 0x0 37 gst 0x008e go sleep time register [15:0] 0x0 38 ? 0x0 39 0x0 38 0x0 39 ctpdc 0x0000 clock tree power down control register [15:0] 0x03a C 0x04b 0x0 3a 0x0 4b reserved (18 ? byte s) dont c are none 0x04c C 0x04d 0x0 4c 0x0 4d p1mbcr 0x3120 phy 1 and mii basic control register [15:0] 0x04e C 0x04f 0x0 4e 0x0 4f p1mbsr 0x7808 phy 1 and mii basic status register [15:0] 0x050 ? 0x05 1 0x05 0 0x05 1 phy1ilr 0x1430 phy 1 phyid low register [15:0] 0x052 ? 0x05 3 0x05 2 0x05 3 phy1ihr 0x0022 phy 1 phyid high register [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 90 revision 1.0 internal i/o register space mapping for switch control and co nfiguration (0x000 C 0x0ff) (continued) i/o register offset location re gister name default value description 16 ? bit 8 ? bit 0x0 54 ? 0x0 55 0x0 54 0x0 55 p1anar 0x05e1 phy 1 auto?negotiation advertisement register [15:0] 0x0 56 ? 0x0 57 0x0 56 0x0 57 p1anlpr 0x0001 phy 1 auto?negotiation link partner ability register [15:0] 0x0 58 ? 0x0 59 0x0 58 0x0 59 p2mbcr 0x3120 phy 2 and mii basic control register [15:0] 0x0 5a ? 0x0 5b 0x0 5a 0x0 5b p2mbsr 0x7808 phy 2 and mii basic status register [15:0] 0x05c ? 0x05d 0x05c 0x05d phy2 ilr 0x1430 phy 2 phyid low register [15:0] 0x05e ? 0x05f 0x05e 0x05f phy2 ihr 0x0022 phy 2 phyid high register [15:0] 0x0 60 ? 0x0 61 0x0 60 0x0 61 p2anar 0x05e1 phy 2 auto?negotiation advertisement register [15:0] 0x0 62 ? 0x0 63 0x0 62 0x0 63 p2anlpr 0x0001 phy 2 auto?negotiation link partner ability register [15:0] 0x0 64 ? 0x0 65 0x0 64 0x0 65 reserved (2?bytes) dont care none 0x0 66 ? 0x0 67 0x0 66 0x0 67 p1phyctrl 0x0004 phy 1 special control and status register [15:0] 0x0 68 ? 0x0 69 0x0 68 0x0 69 reserved (2?bytes) dont care none 0x0 6a ? 0x0 6b 0x0 6a 0x0 6b p2 phyctrl 0x0004 phy 2 special control and status register [15:0] 0x0 6c ? 0x0 6d 0x0 6c 0x0 6d p1cr1 0x0000 port 1 control register 1 [15:0] 0x0 6e ? 0x0 6f 0x0 6e 0x0 6f p1cr2 0x0607 port 1 control register 2 [15:0] 0x0 70 ? 0x0 71 0x0 70 0x0 71 p1vidcr 0x0001 port 1 vid control register [15:0] 0x0 72 ? 0x0 73 0x0 72 0x0 73 p1cr 3 0x0000 port 1 control register 3 [15:0] 0x0 74 ? 0x0 75 0x0 74 0x0 75 p1ircr 0 0x0000 port 1 ingress rate control register 0 [15:0] 0x0 76 ? 0x0 77 0x0 76 0x0 77 p1ircr 1 0x0000 port 1 ingress rate control register 1 [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 91 revision 1.0 internal i/o register space mapping for switch control and co nfiguration (0x000 C 0x0ff) (continued) i/o register offset location re gister name default value description 16 ? bit 8 ? bit 0x0 78 ? 0x0 79 0x0 78 0x0 79 p1e rcr 0 0x0000 port 1 e gress rate control register 0 [15:0] 0x0 7a ? 0x0 7b 0x0 7a 0x0 7b p1e rcr 1 0x0000 port 1 e gress rate control register 1 [15:0] 0x0 7c ? 0x0 7d 0x0 7c 0x0 7d p1scslmd 0x0 4 00 port 1 phy special control/status, linkmd ? register [15:0] 0x0 7e ? 0x0 7f 0x0 7e 0x0 7f p1cr 4 0x00ff port 1 control register 4 [15:0] 0x0 80 ? 0x0 81 0x0 80 0x0 81 p1sr 0x8000 port 1 status register [15:0] 0x0 82 ? 0x0 83 0x0 82 0x0 83 reserved (2?bytes) dont c are none 0x0 84 ? 0x0 85 0x0 84 0x0 85 p2 cr1 0x0000 port 2 control register 1 [15:0] 0x0 86 ? 0x0 87 0x0 86 0x0 87 p2 cr2 0x0607 port 2 control register 2 [15:0] 0x0 88 ? 0x0 89 0x0 88 0x0 89 p2 vidcr 0x0001 port 2 vid control register [15:0] 0x0 8a ? 0x0 8b 0x0 8a 0x0 8b p2 cr 3 0x0000 port 2 control register 3 [15:0] 0x0 8c ? 0x0 8d 0x0 8c 0x0 8d p2 ircr 0 0x0000 port 2 ingress rate control register 0 [15:0] 0x0 8e ? 0x0 8f 0x0 8e 0x0 8f p2 ircr 1 0x0000 port 2 ingress rate control register 1 [15:0] 0x0 90 ? 0x0 91 0x0 90 0x0 91 p2e rcr 0 0x0000 port 2 e gress rate control register 0 [15:0] 0x0 92 ? 0x0 93 0x0 92 0x0 93 p2e rcr 1 0x0000 port 2 e gress rate control register 1 [15:0] 0x0 94 ? 0x0 95 0x0 94 0x0 95 p2scslmd 0x0 4 00 port 2 phy special control/status, linkmd register [15:0] 0x0 96 ? 0x0 97 0x0 96 0x0 97 p2 cr 4 0x00ff port 2 control register 4 [15:0] 0x0 98 ? 0x0 99 0x0 98 0x0 99 p2sr 0x8000 port 2 status register [15:0] 0x0 9a ? 0x0 9b 0x0 9a 0x0 9b reserved (2?bytes) dont care none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 92 revision 1.0 internal i/o register space mapping for switch control and co nfiguration (0x000 C 0x0ff) (continued) i/o register offset location re gister name default value description 16 ? bit 8 ? bit 0x0 9c ? 0x0 9d 0x0 9c 0x0 9d p3 cr1 0x0000 port 3 control register 1 [15:0] 0x0 9e ? 0x0 9f 0x0 9e 0x0 9f p3 cr2 0x0607 port 3 control register 2 [15:0] 0x0 a0 ? 0x0 a1 0x0 a0 0x0 a1 p3 vidcr 0x0001 port 3 vid control register [15:0] 0x0 a2 ? 0x0 a3 0x0 a2 0x0 a3 p3 cr 3 0x0000 port 3 control register 3 [15:0] 0x0 a4 ? 0x0 a5 0x0 a4 0x0 a5 p3 ircr 0 0x0000 port 3 ingress rate control register 0 [15:0] 0x0 a6 ? 0x0 a7 0x0 a6 0x0 a7 p3 ircr 1 0x0000 port 3 ingress rate control register 1 [15:0] 0x0 a8 ? 0x0 a9 0x0 a8 0x0 a9 p3e rcr 0 0x0000 port 3 e gress rate control register 0 [15:0] 0x0 aa ? 0x0 ab 0x0 aa 0x0 ab p3e rcr 1 0x0000 port 3 e gress rate control register 1 [15:0] 0x0 ac ? 0x0 ad 0x0 ac 0x0 ad sgcr8 0x8000 switch global control register 8 [15:0] 0x0 ae ? 0x0 af 0x0 ae 0x0 af sgcr9 0x0000 switch global control register 9 [15:0] 0x0 b0 ? 0x0 b1 0x0 b0 0x0 b1 safmaca1l 0x0000 source address filtering mac address 1 register low [15:0] 0x0 b2 ? 0x0 b3 0x0 b2 0x0 b3 safmaca1m 0x0000 source address filtering mac address 1 register middle [15:0] 0x0 b4 ? 0x0 b5 0x0 b4 0x0 b5 safmaca1h 0x0000 source address filtering mac address 1 register high [15:0] 0x0 b6 ? 0x0 b7 0x0 b6 0x0 b7 safmaca2l 0x0000 source address filtering mac address 2 register low [15:0] 0x0 b8 ? 0x0 b9 0x0 b8 0x0 b9 safmaca2m 0x0000 source address filtering mac address 2 register middle [15:0] 0x0 ba ? 0x0 bb 0x0 ba 0x0 bb safmaca2h 0x0000 source address filtering mac address 2 register high [15:0] 0x0 bc ? 0x0 c7 0x0 bc 0x0 c7 reserved (12?bytes) dont c are none 0x0 c8 ? 0x0 c9 0x0 c8 0x0 c9 p1txqrcr1 0x8488 port 1 txq rate control register 1 [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 93 revision 1.0 internal i/o register space mapping for switch control and co nfiguration (0x000 C 0x0ff) (continued) i/o register offset location re gister name default value description 16 ? bit 8 ? bit 0x0 ca ? 0x0 cb 0x0 ca 0x0 cb p1txqrcr2 0x8182 port 1 txq rate control register 2 [15:0] 0x0 cc ? 0x0 cd 0x0 cc 0x0 cd p2txqrcr1 0x8488 port 2 txq rate control register 1 [15:0] 0x0 ce ? 0x0 cf 0x0 ce 0x0 cf p2txqrcr2 0x8182 port 2 txq rate control register 2 [15:0] 0x0 d0 ? 0x0 d1 0x0 d0 0x0 d1 p3txqrcr1 0x8488 port 3 txq rate control register 1 [15:0] 0x0 d2 ? 0x0 d3 0x0 d2 0x0 d3 p3txqrcr2 0x8182 port 3 txq rate control register 2 [15:0] 0x0 d4 ? 0x0 d5 0x 0d4 0x 0d5 reserved (2?bytes) dont c are none 0x0d6 ? 0x0d7 0x 0 d6 0x 0 d7 iomxsel 0x0fff input and output multiplex selection register [15:0] 0x0d8 ? 0x0d9 0x 0d8 0x 0d9 cfgr 0x00fe configuration status and serial bus mode register 0x0da ? 0x0db 0x 0da 0x 0db reserved (2?bytes) dont care none 0x0dc ? 0x0dd 0x 0dc 0x 0dd p1anpt 0x2001 port 1 auto?negotiation next page t ransmit r egister [15:0] 0x0de ? 0x0df 0x 0de 0x 0df p1alprnp 0x0000 port 1 auto?negotiation link partner received next page r egister [15:0] 0x0 e0 ? 0x0 e1 0x0 e0 0x0 e1 p1eeea 0x0002 port 1 eee and link partner advertisement register [15:0] 0x0 e2 ? 0x0 e3 0x0 e2 0x0 e3 p1eeewec 0x0000 port 1 eee wake error count register [15:0] 0x0 e4 ? 0x0 e5 0x0 e4 0x0 e5 p1eeecs 0x8064 port 1 eee control/status and auto?negotiation expansion register [15:0] 0x0 e6 ? 0x0 e7 0x0 e6 0x0 e7 p1lpirtc bl2lpic1 0x27 0x08 port 1 lpi recovery time counter register [7:0] buffer load to lpi control 1 register [7:0] 0x0 e8 ? 0x0 e9 0x0 e8 0x0 e9 p2anpt 0x2001 port 2 auto?negotiation next page t ransmit r egister [15:0] 0x0 ea ? 0x0 eb 0x0 ea 0x0 eb p2alprnp 0x0000 port 2 auto?negotiation link partner received next page r egister [15:0] 0x0 ec ? 0x0 ed 0x0 ec 0x0 ed p2eeea 0x0002 port 2 eee and link partner advertisement register [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 94 revision 1.0 internal i/o register space mapping for switch control and co nfiguration (0x000 C 0x0ff) (continued) i/o register offset location re gister name default value description 16 ? bit 8 ? bit 0x0 ee ? 0x0 ef 0x0 ee 0x0 ef p2eeewec 0x0000 port 2 eee wake error count register [15:0] 0x0 f0 ? 0x0 f1 0x0 f0 0x0 f1 p2eeecs 0x8064 port 2 eee control/status and auto?negotiation expansion register [15:0] 0x0 f2 ? 0x0 f3 0x0 f2 0x0 f3 p2lpirtc pcseeec 0x27 0x03 port 2 lpi recovery time counter register [7:0] pcs eee control register [7:0] 0x0 f4 ? 0x0 f5 0x0 f4 0x0 f5 etlwtc 0x03e8 empty txq to lpi wait time control register [15:0] 0x0 f6 ? 0x0 f7 0x0 f6 0x0 f7 bl2lpic2 0xc040 buffer load to lpi control 2 register [15:0] 0x0f8 ? 0x0ff 0x 0f8 0x 0ff reserved (8?bytes) dont care none internal i/o register space mapping for host interface unit (0x 100 C 0x16f) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x100 C 0x1 07 0x100 0x107 reserved (8? byte s) dont c are none 0x108 ? 0x109 0x108 0x109 ccr read only chip configuration register [15 :0] 0x10a ? 0x10f 0x10a 0x10f reserved (6 ? byte s) dont c are none 0x110 ? 0x111 0x110 0x111 marl ? mac address register low [15 :0] 0x112 ? 0x113 0x112 0x113 marm ? m ac address register middle [15:0] 0x114 ? 0x115 0x114 0x115 marh ? mac address registe r high [15:0 ] 0x116 ? 0x121 0x116 0x121 reserved (12 ? byte s) dont c are none 0x122 ? 0x123 0x122 0x123 eepcr 0x0000 eeprom control register [15:0 ] 0x124 ? 0x125 0x124 0x125 mbir 0x 0000 memory bist info register [15:0 ] 0x126 ? 0x127 0x126 0x127 grr 0x0000 global reset register [15:0 ] 0x128 ? 0x129 0x128 0x129 reserved (2? byte s) dont c are none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 95 revision 1.0 internal i/o register space mapping for host interface unit (0x 100 C 0x16 f) (continued) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x12a ? 0x12b 0x12a 0x12b wfcr 0x0000 wake - up f rame control register [15:0 ] 0x12c ? 0x12f 0x12c 0x12f reserved (4 ? byte s) dont c are none 0x130 ? 0x131 0x130 0x131 wf0crc0 0x0000 wake - up frame 0 crc0 register [15:0 ] 0x132 ? 0x133 0x132 0x133 wf0crc1 0x0000 wake - up frame 0 crc1 register [15:0 ] 0x134 ? 0x135 0x134 0x135 wf0bm0 0x0000 wake - up fr ame 0 byte mask 0 register [15:0 ] 0x136 ? 0x137 0x136 0x137 wf0bm1 0x0000 wake - up fr ame 0 byte mask 1 register [15:0 ] 0x138 ? 0x139 0x138 0x139 wf0bm2 0x0000 wake - up fr ame 0 byte mask 2 register [15:0 ] 0x13a ? 0x13b 0x13a 0x13b wf0bm3 0x0000 wake - up fr ame 0 byte mask 3 register [15:0 ] 0x13c ? 0x13f 0x13c 0x13f reserved (4 ? byte s) dont care none 0x140 ? 0x141 0x140 0x141 wf1crc0 0x0000 wake - up frame 1 crc0 register [15:0 ] 0x142 ? 0x143 0x142 0x143 wf1crc1 0x0000 wake - up frame 1 crc1 register [15:0 ] 0x144 ? 0x145 0x144 0x145 wf1bm0 0x0000 wake - up fr ame 1 byte mask 0 register [15:0 ] 0x146 ? 0x147 0x146 0x147 wf1bm1 0x0000 wake - up fr ame 1 byte mask 1 register [15:0 ] 0x148 ? 0x149 0x148 0x149 wf1bm2 0x0000 wake - up fr ame 1 byte mask 2 register [15:0 ] 0x14a ? 0x14b 0x14a 0x14b wf1bm3 0x0000 wake - up fr ame 1 byte mask 3 register [15:0 ] 0x14c ? 0x14f 0x14c 0x14f reserved (4 ? byte s) dont c are none 0x150 ? 0x151 0x150 0x151 wf2crc0 0x0000 wake - up fra me 2 crc0 register [15:0 ] 0x152 ? 0x153 0x152 0x153 wf2crc1 0x0000 wake - up frame 2 crc1 register [15:0 ] 0x154 ? 0x155 0x154 0x155 wf2bm0 0x0000 wake - up frame 2 byte ma sk 0 register [15:0 ] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 96 revision 1.0 internal i/o register space mapping for host interface unit (0x 100 C 0x16 f) (continued) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x156 ? 0x157 0x156 0x157 wf2bm1 0x0000 wake - up fr ame 2 byte mask 1 register [15:0 ] 0x158 ? 0x159 0x158 0x159 wf2bm2 0x0000 wake - up frame 2 byte mask 2 register [15:0 ] 0x15a ? 0x15b 0x15a 0x15b wf2bm3 0x0000 wake - up fr ame 2 byte mask 3 register [15:0 ] 0x15c ? 0x15f 0x15c 0x15f reserved (4 ? byte s) dont c are none 0x160 ? 0x161 0x160 0x161 wf3crc0 0x0000 wake - up frame 3 crc0 register [15:0 ] 0x162 ? 0x163 0x162 0x163 wf3crc1 0x0000 wake - up frame 3 crc1 register [15:0 ] 0x164 ? 0x165 0x164 0x165 wf3bm0 0x0000 wake - up fr ame 3 byte mask 0 register [15:0 ] 0x166 ? 0x167 0x166 0x167 wf3bm1 0x0000 wake - up fr ame 3 byte mask 1 register [15:0 ] 0x168 ? 0x169 0x168 0x169 wf3bm2 0x0000 wake - up fr ame 3 byte mask 2 register [15:0 ] 0x16a ? 0x16b 0x16a 0x16b wf3bm3 0x0000 wake - up fr ame 3 byte mask 3 register [15:0 ] 0x16c ? 0x16f 0x16c 0x16f reserved (4 ? byte s) dont c are none internal i/o register space mapping for the qmu (0x170 ? 0x1ff) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x170 ? 0x171 0x170 0x171 txcr 0x0000 transmit control register [15:0 ] 0x172 ? 0x173 0x172 0x173 txsr 0x0000 transmit status register [15:0 ] 0x174 ? 0x175 0x174 0x175 rxcr1 0x0800 rece ive control register 1 [15:0 ] 0x176 ? 0x177 0x176 0x177 rxcr2 0x011 4 receive control register 2 [15:0 ] 0x178 ? 0x179 0x178 0x179 txmir 0x1800 txq m emory information register [15:0 ] 0x17a ? 0x17b 0x17a 0x17b reserved dont c are none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 97 revision 1.0 internal i/o register space mapping for the qmu (0x170 ? 0x1ff) (continued) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x17c ? 0x17d 0x17c 0x17d rxfhsr 0x0000 receive frame header status register [15:0 ] 0x17e ? 0x17f 0x17e 0x17f rxfhbcr 0x0000 receive frame header byte count register [15:0 ] 0x180 ? 0x181 0x180 0x181 txqcr 0x0000 txq command register [15:0 ] 0x182 ? 0x183 0x182 0x183 rxqcr 0x0000 rxq command register [15:0 ] 0x184 ? 0x185 0x184 0x185 txfdpr 0x0000 tx f rame data pointer register [15:0 ] 0x186 ? 0x187 0x186 0x187 rxfdpr C rx f rame data pointer register [15:0 ] 0x188 ? 0x18b 0x188 0x18b reserved (4 ? byte s) dont c are none 0x18c ? 0x18d 0x18c 0x18d rxdttr 0x0000 rx duratio n timer threshold register [15:0 ] 0x18e ? 0x18f 0x18e 0x18f rxdbctr 0x0000 rx data byte count threshold register [15:0 ] 0x190 ? 0x191 0x190 0x191 ier 0x0000 interrupt enable register [15:0 ] 0x192 ? 0x193 0x192 0x193 isr 0x0 0 00 interrupt status register [15:0 ] 0x194 ? 0x19b 0x194 0x19b reserved (8 ? byte s) dont c are none 0x19c ? 0x19d 0x19c 0x19d rxfc tr 0x0000 rx frame count threshold register [7:0 ] , 15:8 are reserved 0x19e ? 0x19f 0x19e 0x19f txntfsr 0x0000 tx next total frames size register [15:0 ] 0x1a0 ? 0x1a1 0x1a0 0x1a1 mahtr0 0x0000 mac add ress hash table register 0 [15:0 ] 0x1a2 ? 0x1a3 0x1a2 0x1a3 mahtr1 0x0000 mac address h ash table register 1 [15:0 ] 0x1a4 ? 0x1a5 0x1a4 0x1a5 mahtr2 0x0000 mac add ress hash table register 2 [15:0 ] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 98 revision 1.0 internal i/o register space mapping for the qmu (0x170 ? 0x1ff) (continued) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x1a6 ? 0x1a7 0x1a6 0x1a7 mahtr3 0x0000 mac address hash table register 3 [15:0 ] 0x1a8 ? 0x1af 0x1a8 0x1af reserved (8 ? byte s) d ont c are none 0x1b0 ? 0x1b1 0x1b0 0x1b1 fclwr 0x0 6 00 flow cont rol low water mark register [15:0 ] 0x1b2 ? 0x1b3 0x1b2 0x1b3 fchwr 0x0 4 00 flow control high water mark register [15:0 ] 0x1b4 ? 0x1b5 0x1b4 0x1b5 fcowr 0x0040 flow control overrun water mark register [15:0 ] 0x 1b6 ? 0x1 b7 0x1b6 0x1b7 reserved (2?bytes) d ont c are none 0x1 b8 ? 0x1 b9 0x1 b8 0x1 b9 rxfc 0x00 rx frame count[15:8 ], reserved [7:0] 0x 1ba ? 0x1ff 0x1 ba 0x1ff reserved (70?bytes) d ont c are none internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x200 ? 0x201 0x200 0x201 trig_err 0x0000 trigger output unit error register [11:0] 0x202 ? 0x203 0x202 0x203 trig_active 0x0000 trigger output unit active register [11:0] 0x204 ? 0x205 0x204 0x205 trig_done 0x0000 trigger output unit done register [11:0] 0x206 ? 0x207 0x206 0x207 trig_en 0x0000 trigger output unit enable register [11:0] 0x208 ? 0x209 0x208 0x209 trig_sw_rst 0x0000 trigger output unit software reset register [11:0] 0x20a ? 0x20b 0x20a 0x20b trig12_pps_width 0x0000 trigger output unit 12 pps pulse width register 0x20c C 0x21f 0x20c 0x21f reserved (20 ? byte s) dont care none 0x220 ? 0x221 0x220 0x221 trig1_tgt_nsl 0x0000 trigger ouput unit 1 target time in nanosecond s low ? word register [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 99 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x222 ? 0x223 0x222 0x223 trig1_tgt_nsh 0x0000 trigger output unit 1 target time in nanosecond s high ? word register [29:16] 0x224 ? 0x225 0x224 0x225 trig1_tgt_sl 0x0000 trigger output unit 1 target time in second s low ? word register [15:0] 0x226 ? 0x227 0x226 0x227 trig1_tgt_sh 0x0000 trigger output unit 1 target time in second s high ? word register [31:16] 0x228 ? 0x229 0x228 0x229 trig1_cfg_1 0x3c00 trigger output unit 1 configuration/control register1 0x22a ? 0x22b 0x22a 0x22b trig1_cfg_2 0x0000 trigger output unit 1 configuration/control register2 0x22c ? 0x22d 0x22c 0x22d trig1_cfg_3 0x0000 trigger output unit 1 configuration/control register3 0x22e ? 0x22f 0x22e 0x22f trig1_cfg_4 0x0000 trigger output unit 1 configuration/control register4 0x230 ? 0x231 0x230 0x231 trig1_cfg_5 0x0000 trigger output unit 1 configuration/control register5 0x232 ? 0x233 0x232 0x233 trig1_cfg_6 0x0000 trigger output unit 1 configuration/control register6 0x234 ? 0x235 0x234 0x235 trig1_cfg_7 0x0000 trigger output unit 1 configuration/control register7 0x236 ? 0x237 0x236 0x237 trig1_cfg_8 0x0000 trigger output unit 1 configuration/control register8 0x238 C 0x23f 0x238 0x23f reserved (8 ? byte s) dont c are none 0x240 ? 0x241 0x240 0x241 trig2_tgt_nsl 0x0000 trigger output unit 2 target time in nanosecond s low ? word register [15:0] 0x242 ? 0x243 0x242 0x243 trig2_tgt_nsh 0x0000 trigger output unit 2 target time in nanosecond s high ? word register [29:16] 0x244 ? 0x245 0x244 0x245 trig2_tgt_sl 0x0000 trigger output unit 2 target time in second s low ? word register [15:0] 0x246 ? 0x247 0x246 0x247 trig2_tgt_sh 0x0000 trigger output unit 2 target time in second s high ? word register [31:16] 0x248 ? 0x249 0x248 0x249 trig2_cfg_1 0x3c00 trigger output unit 2 configuration/control register1 0x24a ? 0x24b 0x24a 0x24b trig2_cfg_2 0x0000 trigger output unit 2 configuration/control register2 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 100 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x24c ? 0x24d 0x24c 0x24d trig2_cfg_3 0x0000 trigger output unit 2 configuration/control register3 0x24e ? 0x24f 0x24e 0x24f trig2_cfg_4 0x0000 trigger output unit 2 configuration/control register4 0x250 ? 0x251 0x250 0x251 trig2_cfg_5 0x0000 trigger output unit 2 configuration/control register5 0x252 ? 0x253 0x252 0x253 trig2_cfg_6 0x0000 trigger output unit 2 configuration/control register6 0x254 ? 0x255 0x254 0x255 trig2_cfg_7 0x0000 trigger output unit 2 configuration/control register7 0x256 ? 0x257 0x256 0x257 trig2_cfg_8 0x0000 trigger output unit 2 configuration/control register8 0x258 C 0x25f 0x258 0x25f reserved (8 ? byte s) dont c are none 0x260 ? 0x261 0x260 0x261 trig3_tgt_nsl 0x0000 trigger output unit 3 target time in nanosecond s low ? word register [15:0] 0x262 ? 0x263 0x262 0x263 trig3_tgt_nsh 0x0000 trigger output unit 3 target time in nanosecond s high ? word register [29:16] 0x264 ? 0x265 0x264 0x265 trig3_tgt_sl 0x0000 trigger output unit 3 target time in second s low ? word register [15:0] 0x266 ? 0x267 0x266 0x267 trig3_tgt_sh 0x0000 trigger output unit 3 target time in second s high ? word register [31:16] 0x268 ? 0x269 0x268 0x269 trig3_cfg_1 0x3c00 trigger output unit 3 configuration/control register1 0x26a ? 0x26b 0x26a 0x26b trig3_cfg_2 0x0000 trigger output unit 3 configuration/control register2 0x26c ? 0x26d 0x26c 0x26d trig3_cfg_3 0x0000 trigger output unit 3 configuration/control register3 0x26e ? 0x26f 0x26e 0x26f trig3_cfg_4 0x0000 trigger output unit 3 configuration/control register4 0x270 ? 0x271 0x270 0x271 trig3_cfg_5 0x0000 trigger output unit 3 configuration/control register5 0x272 ? 0x273 0x272 0x273 trig3_cfg_6 0x0000 trigger output unit 3 configuration/control register6 0x274 ? 0x275 0x274 0x275 trig3_cfg_7 0x0000 trigger output unit 3 configuration/control register7 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 101 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x276 ? 0x277 0x276 0x277 trig3_cfg_8 0x0000 trigger output unit 3 configuration/control register8 0x278 C 0x27f 0x278 0x27f reserved (8 ? byte s) dont c are none 0x280 ? 0x281 0x280 0x281 trig4_tgt_nsl 0x0000 trigger output unit 4 target time in nanosecond s low ? word register [15:0] 0x282 ? 0x283 0x282 0x283 trig4_tgt_nsh 0x0000 trigger output unit 4 target time in nanosecond s high ? word register [29:16] 0x284 ? 0x285 0x284 0x285 trig4_tgt_sl 0x0000 trigger output unit 4 target time in second s low ? word register [15:0] 0x286 ? 0x287 0x286 0x287 trig4_tgt_sh 0x0000 trigger output unit 4 target time in second s high ? word register [31:16] 0x288 ? 0x289 0x288 0x289 trig4_cfg_1 0x3c00 trigger output unit 4 configuration/control register1 0x28a ? 0x28b 0x28a 0x28b trig4_cfg_2 0x0000 trigger output unit 4 configuration/control register2 0x28c ? 0x28d 0x28c 0x28d trig4_cfg_3 0x0000 trigger output unit 4 configuration/control register3 0x28e ? 0x28f 0x28e 0x28f trig4_cfg_4 0x0000 trigger output unit 4 configuration/control register4 0x290 ? 0x291 0x290 0x291 trig4_cfg_5 0x0000 trigger output unit 4 configuration/control register5 0x292 ? 0x293 0x292 0x293 trig4_cfg_6 0x0000 trigger output unit 4 configuration/control register6 0x294 ? 0x295 0x294 0x295 trig4_cfg_7 0x0000 trigger output unit 4 configuration/control register7 0x296 ? 0x297 0x296 0x297 trig4_cfg_8 0x0000 trigger output unit 4 configuration/control register8 0x298 C 0x29f 0x298 0x29f reserved (8 ? byte s) dont c are none 0x2a0 ? 0x2a1 0x2a0 0x2a1 trig5_tgt_nsl 0x0000 trigger output unit 5 target time in nanosecond s low ? word register [15:0] 0x2a2 ? 0x2a3 0x2a2 0x2a3 trig5_tgt_nsh 0x0000 trigger output unit 5 target time in nanosecond s high ? word register [29:16] 0x2a4 ? 0x2a5 0x2a4 0x2a5 trig5_tgt_sl 0x0000 trigger output unit 5 target time in second s low ? word register [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 102 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x2a6 ? 0x2a7 0x2a6 0x2a7 trig5_tgt_sh 0x0000 trigger output unit 5 target time in second s high ? word register [31:16] 0x2a8 ? 0x2a9 0x2a8 0x2a9 trig5_cfg_1 0x3c00 trigger output unit 5 configuration/control register1 0x2aa ? 0x2ab 0x2aa 0x2ab trig5_cfg_2 0x0000 trigger output unit 5 configuration/control register2 0x2ac ? 0x2ad 0x2ac 0x2ad trig5_cfg_3 0x0000 trigger output unit 5 configuration/control register3 0x2ae ? 0x2af 0x2ae 0x2af trig5_cfg_4 0x0000 trigger output unit 5 configuration/control register4 0x2b0 ? 0x2b1 0x2b0 0x2b1 trig5_cfg_5 0x0000 trigger output unit 5 configuration/control register5 0x2b2 ? 0x2b3 0x2b2 0x2b3 trig5_cfg_6 0x0000 trigger output unit 5 configuration/control register6 0x2b4 ? 0x2b5 0x2b4 0x2b5 trig5_cfg_7 0x0000 trigger output unit 5 configuration/control register7 0x2b6 ? 0x2b7 0x2b6 0x2b7 trig5_cfg_8 0x0000 trigger output unit 5 configuration/control register8 0x2b8 C 0x2bf 0x2b8 0x2bf reserved (8 ? byte s) dont c are none 0x2c0 ? 0x2c1 0x2c0 0x2c1 trig6_tgt_nsl 0x0000 trigger output unit 6 target time in nanosecond s low ? word register [15:0] 0x2c2 ? 0x2c3 0x2c2 0x2c3 trig6_tgt_nsh 0x0000 trigger output unit 6 target time in nanosecond s high ? word register [29:16] 0x2c4 ? 0x2c5 0x2c4 0x2c5 trig6_tgt_sl 0x0000 trigger output unit 6 target time in second s low ? word register [15:0] 0x2c6 ? 0x2c7 0x2c6 0x2c7 trig6_tgt_sh 0x0000 trigger output unit 6 target time in second s high ? word register [31:16] 0x2c8 ? 0x2c9 0x2c8 0x2c9 trig6_cfg_1 0x3c00 trigger output unit 6 configuration/control register1 0x2ca ? 0x2cb 0x2ca 0x2cb trig6_cfg_2 0x0000 trigger output unit 6 configuration/control register2 0x2cc ? 0x2cd 0x2cc 0x2cd trig6_cfg_3 0x0000 trigger output unit 6 configuration/control register3 0x2ce ? 0x2cf 0x2ce 0x2cf trig6_cfg_4 0x0000 trigger output unit 6 configuration/control register4 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 103 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x2d0 ? 0x2d1 0x2d0 0x2d1 trig6_cfg_5 0x0000 trigger output unit 6 configuration/control register5 0x2d2 ? 0x2d3 0x2d2 0x2d3 trig6_cfg_6 0x0000 trigger output unit 6 configuration/control register6 0x2d4 ? 0x2d5 0x2d4 0x2d5 trig6_cfg_7 0x0000 trigger output unit 6 configuration/control register7 0x2d6 ? 0x2d7 0x2d6 0x2d7 trig6_cfg_8 0x0000 trigger output unit 6 configuration/control register8 0x2d8 C 0x2df 0x2d8 0x2df reserved (8 ? byte s) dont c are none 0x2e0 ? 0x2e1 0x2e0 0x2e1 trig7_tgt_nsl 0x0000 trigger output unit 7 target time in nanosecond s low ? word register [15:0] 0x2e2 ? 0x2e3 0x2e2 0x2e3 trig7_tgt_nsh 0x0000 trigger output unit 7 target time in nanosecond s high ? word register [29:16] 0x2e4 ? 0x2e5 0x2e4 0x2e5 trig7_tgt_sl 0x0000 trigger output unit 7 target time in second s low ? word register [15:0] 0x2e6 ? 0x2e7 0x2e6 0x2e7 trig7_tgt_sh 0x0000 trigger output unit 7 target time in second s high ? word register [31:16] 0x2e8 ? 0x2e9 0x2e8 0x2e9 trig7_cfg_1 0x3c00 trigger output unit 7 configuration/control register1 0x2ea ? 0x2eb 0x2ea 0x2eb trig7_cfg_2 0x0000 trigger output unit 7 configuration/control register2 0x2ec ? 0x2ed 0x2ec 0x2ed trig7_cfg_3 0x0000 trigger output unit 7 configuration/control register3 0x2ee ? 0x2ef 0x2ee 0x2ef trig7_cfg_4 0x0000 trigger output unit 7 configuration/control register4 0x2f0 ? 0x2f1 0x2f0 0x2f1 trig7_cfg_5 0x0000 trigger output unit 7 configuration/control register5 0x2f2 ? 0x2f3 0x2f2 0x2f3 trig7_cfg_6 0x0000 trigger output unit 7 configuration/control register6 0x2f4 ? 0x2f5 0x2f4 0x2f5 trig7_cfg_7 0x0000 trigger output unit 7 configuration/control register7 0x2f6 ? 0x2f7 0x2f6 0x2f7 trig7_cfg_8 0x0000 trigger output unit 7 configuration/control register8 0x2f8 C 0x2ff 0x2f8 0x2ff reserved (8 ? byte s) dont c are none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 104 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x300 ? 0x301 0x300 0x301 trig8_tgt_nsl 0x0000 trigger output unit 8 target time in nanosecond s low ? word register [15:0] 0x302 ? 0x303 0x302 0x303 trig8_tgt_nsh 0x0000 trigger output unit 8 target time in nanosecond s high ? word register [29:16] 0x304 ? 0x305 0x304 0x305 trig8_tgt_sl 0x0000 trigger output unit 8 target time in second s low ? word register [15:0] 0x306 ? 0x307 0x306 0x307 trig8_tgt_sh 0x0000 trigger output unit 8 target time in second s high ? word register [31:16] 0x308 ? 0x309 0x308 0x309 trig8_cfg_1 0x3c00 trigger output unit 8 configuration/control register1 0x30a ? 0x30b 0x30a 0x30b trig8_cfg_2 0x0000 trigger output unit 8 configuration/control register2 0x30c ? 0x30d 0x30c 0x30d trig8_cfg_3 0x0000 trigger output unit 8 configuration/control register3 0x30e ? 0x30f 0x30e 0x30f trig8_cfg_4 0x0000 trigger output unit 8 configuration/control register4 0x310 ? 0x311 0x310 0x311 trig8_cfg_5 0x0000 trigger output unit 8 configuration/control register5 0x312 ? 0x313 0x312 0x313 trig8_cfg_6 0x0000 trigger output unit 8 configuration/control register6 0x314 ? 0x315 0x314 0x315 trig8_cfg_7 0x0000 trigger output unit 8 configuration/control register7 0x316 ? 0x317 0x316 0x317 trig8_cfg_8 0x0000 trigger output unit 8 configuration/control register8 0x318 C 0x31f 0x318 0x31f reserved (8 ? byte s) dont c are none 0x320 ? 0x321 0x320 0x321 trig9_tgt_nsl 0x0000 trigger output unit 9 target time in nanosecond s low ? word register [15:0] 0x322 ? 0x323 0x322 0x323 trig9_tgt_nsh 0x0000 trigger output unit 9 target time in nanosecond s high ? word register [29:16] 0x324 ? 0x325 0x324 0x325 trig9_tgt_sl 0x0000 trigger output unit 9 target time in second s low ? word register [15:0] 0x326 ? 0x327 0x326 0x327 trig9_tgt_sh 0x0000 trigger output unit 9 target time in second s high - word register [31:16] 0x328 ? 0x329 0x328 0x329 trig9_cfg_1 0x3c00 trigger output unit 9 configuration/control register1 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 105 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x32a ? 0x32b 0x32a 0x32b trig9_cfg_2 0x0000 trigger output unit 9 configuration/control register2 0x32c ? 0x32d 0x32c 0x32d trig9_cfg_3 0x0000 trigger output unit 9 configuration/control register3 0x32e ? 0x32f 0x32e 0x32f trig9_cfg_4 0x0000 trigger output unit 9 configuration/control register4 0x330 ? 0x331 0x330 0x331 trig9_cfg_5 0x0000 trigger output unit 9 configuration/control register5 0x332 ? 0x333 0x332 0x333 trig9_cfg_6 0x0000 trigger output unit 9 configuration/control register6 0x334 ? 0x335 0x334 0x335 trig9_cfg_7 0x0000 trigger output unit 9 configuration/control register7 0x336 ? 0x337 0x336 0x337 trig9_cfg_8 0x0000 trigger output unit 9 configuration/control register8 0x338 C 0x33f 0x338 0x33f reserved (8 ? byte s) dont c are none 0x340 ? 0x341 0x340 0x341 trig10_tgt_nsl 0x0000 trigger output unit 10 target time in nanosecond s low ? w ord register [15:0] 0x342 ? 0x343 0x342 0x343 trig10_tgt_nsh 0x0000 trigger output unit 10 target time in nanosecond s high ? word register [29:16] 0x344 ? 0x345 0x344 0x345 trig10_tgt_sl 0x0000 trigger output unit 10 target time in second s low ? word register [15:0] 0x346 ? 0x347 0x346 0x347 trig10_tgt_sh 0x0000 trigger output unit 10 target time in second s high ? word register [31:16] 0x348 ? 0x349 0x348 0x349 trig10_cfg_1 0x3c00 trigger output unit 10 configuration/control register1 0x34a ? 0x34b 0x34a 0x34b trig10_cfg_2 0x0000 trigger output unit 10 configuration/control register2 0x34c ? 0x34d 0x34c 0x34d trig10_cfg_3 0x0000 trigger output unit 10 configuration/control register3 0x34e ? 0x34f 0x34e 0x34f trig10_cfg_4 0x0000 trigger output unit 10 configuration/control register4 0x350 ? 0x351 0x350 0x351 trig10_cfg_5 0x0000 trigger output unit 10 configuration/control register5 0x352 ? 0x353 0x352 0x353 trig10_cfg_6 0x0000 trigger output unit 10 configuration/control register6 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 106 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x354 ? 0x355 0x354 0x355 trig10_cfg_7 0x0000 trigger output unit 10 configuration/control register7 0x356 ? 0x357 0x356 0x357 trig10_cfg_8 0x0000 trigger output unit 10 configuration/control register8 0x358 C 0x35f 0x358 0x35f reserved (8 ? byte s) dont c are none 0x360 ? 0x361 0x360 0x361 trig11_tgt_nsl 0x0000 trigger output unit 11 target time in nanosecond s low ? word register [15:0] 0x362 ? 0x363 0x362 0x363 trig11_tgt_nsh 0x0000 trigger output unit 11 target time in nanosecond s high ? word register [29:16] 0x364 ? 0x365 0x364 0x365 trig11_tgt_sl 0x0000 trigger output unit 11 target time in second s low ? word register [15:0] 0x366 ? 0x367 0x366 0x367 trig11_tgt_sh 0x0000 trigger output unit 11 target time in second s high ? word register [31:16] 0x368 ? 0x369 0x368 0x369 trig11_cfg_1 0x3c00 trigger output unit 11 configuration/control register1 0x36a ? 0x36b 0x36a 0x36b trig11_cfg_2 0x0000 trigger output unit 11 configuration/control register2 0x36c ? 0x36d 0x36c 0x36d trig11_cfg_3 0x0000 trigger output unit 11 configuration/control register3 0x36e ? 0x36f 0x36e 0x36f trig11_cfg_4 0x0000 trigger output unit 11 configuration/control register4 0x370 ? 0x371 0x370 0x371 trig11_cfg_5 0x0000 trigger output unit 11 configuration/control register5 0x372 ? 0x373 0x372 0x373 trig11_cfg_6 0x0000 trigger output unit 11 configuration/control register6 0x374 ? 0x375 0x374 0x375 trig11_cfg_7 0x0000 trigger output unit 11 configuration/control register7 0x376 ? 0x377 0x376 0x377 trig11_cfg_8 0x0000 trigger output unit 11 configuration/control register8 0x378 C 0x37f 0x378 0x37f reserved (8 ? byte s) dont c are none 0x380 ? 0x381 0x380 0x381 trig12_tgt_nsl 0x0000 trigger output unit 12 target time in nanosecond s low ? word register [15:0] 0x382 ? 0x383 0x382 0x383 trig12_tgt_nsh 0x0000 trigger output unit 12 target time in nanosecond s high ? word register [29:16] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 107 revision 1.0 internal i/o register space mapping for ptp trigger output (12 units, 0x200 C 0x3ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x384 ? 0x385 0x384 0x385 trig12_tgt_sl 0x0000 trigger output unit 12 target time in second s low ? word register [15:0] 0x386 ? 0x387 0x386 0x387 trig12_tgt_sh 0x0000 trigger output unit 12 target time in second s high ? word register [31:16] 0x388 ? 0x389 0x388 0x389 trig12_cfg_1 0x3c00 trigger output unit 12 configuration/control register1 0x38a ? 0x38b 0x38a 0x38b trig12_cfg_2 0x0000 trigger output unit 12 configuration/control register2 0x38c ? 0x38d 0x38c 0x38d trig12_cfg_3 0x0000 trigger output unit 12 configuration/control register3 0x38e ? 0x38f 0x38e 0x38f trig12_cfg_4 0x0000 trigger output unit 12 configuration/control register4 0x390 ? 0x391 0x390 0x391 trig12_cfg_5 0x0000 trigger output unit 12 configuration/control register5 0x392 ? 0x393 0x392 0x393 trig12_cfg_6 0x0000 trigger output unit 12 configuration/control register6 0x394 ? 0x395 0x394 0x395 trig12_cfg_7 0x0000 trigger output unit 12 configuration/control register7 0x396 ? 0x397 0x396 0x397 trig12_cfg_8 0x0000 trigger output unit 12 configuration/control register8 0x398 C 0x3ff 0x398 0x3ff reserved (104 ? byte s) dont c are none internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x400 ? 0x401 0x400 0x401 ts_rdy 0x0000 timestamp input unit ready register [11:0] 0x402 ? 0x403 0x402 0x403 ts_en 0x0000 timestamp input unit enable register [11:0] 0x404 ? 0x405 0x404 0x405 ts_sw_rst 0x0000 timestamp input unit software reset register [11:0] 0x406 C 0x41f 0x406 0x41f reserved (26 ? byte s) dont c are none 0x420 C 0x421 0x420 0x421 ts1_status 0x0000 timestamp input unit 1 status register downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 108 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units , 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x422 C 0x423 0x422 0x423 ts1_cfg 0x0000 timestamp input unit 1 configuration/control register 0x424 C 0x425 0x424 0x425 ts1_smpl1_nsl 0x0000 timestamp unit 1 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x426 C 0x427 0x426 0x427 ts1_smpl1_nsh 0x0000 timestamp unit 1 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x428 C 0x429 0x428 0x429 ts1_smpl1_sl 0x0000 timestamp unit 1 input sample time (1 st ) in second s low ? word register [15:0] 0x42a C 0x42b 0x42a 0x42b ts1_smpl1_sh 0x0000 timestamp unit 1 input sample time (1 st ) in second s high ? word register [31:16] 0x42c C 0x42d 0x42c 0x42d ts1_smpl1_sub_ns 0x0000 timestamp unit 1 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x42e C 0x433 0x42e 0x433 reserved (6 ? byte s) dont c are none 0x434 C 0x435 0x434 0x435 ts1_smpl2_nsl 0x0000 timestamp unit 1 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x436 C 0x437 0x436 0x437 ts1_smpl2_nsh 0x0000 timestamp unit 1 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x438 C 0x439 0x438 0x439 ts1_smpl2_sl 0x0000 timestamp unit 1 input sample time (2nd) in second s low ? word register [15:0] 0x43a C 0x43b 0x43a 0x43b ts1_smpl2_sh 0x0000 timestamp unit 1 input sample time (2nd) in second s high ? word register [31:16] 0x43c C 0x43d 0x43c 0x43d ts1_smpl2_sub_ns 0x0000 timestamp unit 1 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x43e C 0x43f 0x43e 0x43f reserved dont c are none 0x440 C 0x441 0x440 0x441 ts2_status 0x0000 timestamp input unit 2 status register 0x442 C 0x443 0x442 0x443 ts2_cfg 0x0000 timestamp input unit 2 configuration/control register 0x444 C 0x445 0x444 0x445 ts2_smpl1_nsl 0x0000 timestamp unit 2 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x446 C 0x447 0x446 0x447 ts2_smpl1_nsh 0x0000 timestamp unit 2 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x448 C 0x449 0x448 0x449 ts2_smpl1_sl 0x0000 timestamp unit 2 input sample time (1 st ) in second s low ? word register [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 109 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x44a C 0x44b 0x44a 0x44b ts2_smpl1_sh 0x0000 timestamp unit 2 input sample time (1 st ) in second s high ? word register [31:16] 0x44c C 0x44d 0x44c 0x44d ts2_smpl1_sub_ns 0x0000 timestamp unit 2 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x44e C 0x453 0x44e 0x453 reserved (6 ? byte s) dont c are none 0x454 C 0x455 0x454 0x455 ts2_smpl2_nsl 0x0000 timestamp unit 2 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x456 C 0x457 0x456 0x457 ts2_smpl2_nsh 0x0000 timestamp unit 2 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x458 C 0x459 0x458 0x459 ts2_smp2_sl 0x0000 timestamp unit 2 input sample time (2nd) in second s low ? word register [15:0] 0x45a C 0x45b 0x45a 0x45b ts2_smpl2_sh 0x0000 timestamp unit 2 input sample time (2nd) in second s high ? word register [31:16] 0x45c C 0x45d 0x45c 0x45d ts2_smpl2_sub_ns 0x0000 timestamp unit 2 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x45e C 0x45f 0x45e 0x45f reserved dont c are none 0x460 C 0x461 0x460 0x461 ts3_status 0x0000 timestamp input unit 3 status register 0x462 C 0x463 0x462 0x463 ts3_cfg 0x0000 timestamp input unit 3 configuration/control register 0x464 C 0x465 0x464 0x465 ts3_smpl1_nsl 0x0000 timestamp unit 3 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x466 C 0x467 0x466 0x467 ts3_smpl1_nsh 0x0000 timestamp unit 3 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x468 C 0x469 0x468 0x469 ts3_smpl1_sl 0x0000 timestamp unit 3 input sample time (1 st ) in second s low ? word register [15:0] 0x46a C 0x46b 0x46a 0x46b ts3_smpl1_sh 0x0000 timestamp unit 3 input sample time (1 st ) in second s high ? word register [31:16] 0x46c C 0x46d 0x46c 0x46d ts3_smpl1_sub_ns 0x0000 timestamp unit 3 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x46e C 0x473 0x46e 0x473 reserved (6 ? byte s) dont c are none 0x474 C 0x475 0x474 0x475 ts3_smpl2_nsl 0x0000 timestamp unit 3 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x476 C 0x477 0x476 0x477 ts3_smpl2_nsh 0x0000 timestamp unit 3 input sample time (2nd) in nanosecond s high ? word register [29:16] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 110 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x478 C 0x479 0x478 0x479 ts3_smp2_sl 0x0000 timestamp unit 3 input sample time (2nd) in second s low ? word register [15:0] 0x47a C 0x47b 0x47a 0x47b ts3_smpl2_sh 0x0000 timestamp unit 3 input sample time (2nd) in second s high ? word register [31:16] 0x47c C 0x47d 0x47c 0x47d ts3_smpl2_sub_ns 0x0000 timestamp unit 3 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x47e C 0x47f 0x47e 0x47f reserved dont c are none 0x480 C 0x481 0x480 0x481 ts4_status 0x0000 timestamp input unit 4 status register 0x482 C 0x483 0x482 0x483 ts4_cfg 0x0000 timestamp input unit 4 configuration/control register 0x484 C 0x485 0x484 0x485 ts4_smpl1_nsl 0x0000 timestamp unit 4 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x486 C 0x487 0x486 0x487 ts4_smpl1_nsh 0x0000 timestamp unit 4 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x488 C 0x489 0x488 0x489 ts4_smpl1_sl 0x0000 timestamp unit 4 input sample time (1 st ) in second s low ? word register [15:0] 0x48a C 0x48b 0x48a 0x48b ts4_smpl1_sh 0x0000 timestamp unit 4 input sample time (1 st ) in second s high ? word register [31:16] 0x48c C 0x48d 0x48c 0x48d ts4_smpl1_sub_ns 0x0000 timestamp unit 4 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x48e C 0x493 0x48e 0x493 reserved (6 ? byte s) dont c are none 0x494 C 0x495 0x494 0x495 ts4_smpl2_nsl 0x0000 timestamp unit 4 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x496 C 0x497 0x496 0x497 ts4_smpl2_nsh 0x0000 timestamp unit 4 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x498 C 0x499 0x498 0x499 ts4_smp2_sl 0x0000 timestamp unit 4 input sample time (2nd) in second s low ? word register [15:0] 0x49a C 0x49b 0x49a 0x49b ts4_smpl2_sh 0x0000 timestamp unit 4 input sample time (2nd) in second s high ? word register [31:16] 0x49c C 0x49d 0x49c 0x49d ts4_smpl2_sub_ns 0x0000 timestamp unit 4 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x49e C 0x49f 0x49e 0x49f reserved dont c are none 0x4a0 C 0x4a1 0x4a0 0x4a1 ts5_status 0x0000 timestamp input unit 5 status register downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 111 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x4a2 C 0x4a3 0x4a2 0x4a3 ts5_cfg 0x0000 timestamp input unit 5 configuration/control register 0x4a4 C 0x4a5 0x4a4 0x4a5 ts5_smpl1_nsl 0x0000 timestamp unit 5 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x4a6 C 0x4a7 0x4a6 0x4a7 ts5_smpl1_nsh 0x0000 timestamp unit 5 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x4a8 C 0x4a9 0x4a8 0x4a9 ts5_smpl1_sl 0x0000 timestamp unit 5 input sample time (1 st ) in second s low ? word register [15:0] 0x4aa C 0x4ab 0x4aa 0x4ab ts5_smpl1_sh 0x0000 timestamp unit 5 input sample time (1 st ) in second s high ? word register [31:16] 0x4ac C 0x4ad 0x4ac 0x4ad ts5_smpl1_sub_ns 0x0000 timestamp unit 5 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x4ae C 0x4b3 0x4ae 0x4b3 reserved (6 ? byte s) dont c are none 0x4b4 C 0x4b5 0x4b4 0x4b5 ts5_smpl2_nsl 0x0000 timestamp unit 5 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x4b6 C 0x4b7 0x4b6 0x4b7 ts5_smpl2_nsh 0x0000 timestamp unit 5 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x4b8 C 0x4b9 0x4b8 0x4b9 ts5_smp2_sl 0x0000 timestamp unit 5 input sample time (2nd) in second s low ? word register [15:0] 0x4ba C 0x4bb 0x4ba 0x4bb ts5_smpl2_sh 0x0000 timestamp unit 5 input sample time (2nd) in second s high ? word register [31:16] 0x4bc C 0x4bd 0x4bc 0x4bd ts5_smpl2_sub_ns 0x0000 timestamp unit 5 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x4be C 0x4bf 0x4be 0x4bf reserved dont c are none 0x4c0 C 0x4c1 0x4c0 0x4c1 ts6_status 0x0000 timestamp input unit 6 status register 0x4c2 C 0x4c3 0x4c2 0x4c3 ts6_cfg 0x0000 timestamp input unit 6 configuration/control register 0x4c4 C 0x4c5 0x4c4 0x4c5 ts6_smpl1_nsl 0x0000 timestamp unit 6 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x4c6 C 0x4c7 0x4c6 0x4c7 ts6_smpl1_nsh 0x0000 timestamp unit 6 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x4c8 C 0x4c9 0x4c8 0x4c9 ts6_smpl1_sl 0x0000 timestamp unit 6 input sample time (1 st ) in second s low ? word register [15:0] 0x4ca C 0x4cb 0x4ca 0x4cb ts6_smpl1_sh 0x0000 timestamp unit 6 input sample time (1 st ) in second s high ? word register [31:16] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 112 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x4cc C 0x4cd 0x4cc 0x4cd ts6_smpl1_sub_ns 0x0000 timestamp unit 6 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x4ce C 0x4d3 0x4ce 0x4d3 reserved (6 ? byte s) dont c are none 0x4d4 C 0x4d5 0x4d4 0x4d5 ts6_smpl2_nsl 0x0000 timestamp unit 6 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x4d6 C 0x4d7 0x4d6 0x4d7 ts6_smpl2_nsh 0x0000 timestamp unit 6 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x4d8 C 0x4d9 0x4d8 0x4d9 ts6_smp2_sl 0x0000 timestamp unit 6 input sample time (2nd) in second s low ? word register [15:0] 0x4da C 0x4db 0x4da 0x4db ts6_smpl2_sh 0x0000 timestamp unit 6 input sample time (2nd) in second s high ? word register [31:16] 0x4dc C 0x4dd 0x4dc 0x4dd ts6_smpl2_sub_ns 0x0000 timestamp unit 6 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x4de C 0x4df 0x4de 0x4df reserved dont c are none 0x4e0 C 0x4e1 0x4e0 0x4e1 ts7_status 0x0000 timestamp input unit 7 status register 0x4e2 C 0x4e3 0x4e2 0x4e3 ts7_cfg 0x0000 timestamp input unit 7 configuration/control register 0x4e4 C 0x4e5 0x4e4 0x4e5 ts7_smpl1_nsl 0x0000 timestamp unit 7 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x4e6 C 0x4e7 0x4e6 0x4e7 ts7_smpl1_nsh 0x0000 timestamp unit 7 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x4e8 C 0x4e9 0x4e8 0x4e9 ts7_smpl1_sl 0x0000 timestamp unit 7 input sample time (1 st ) in second s low ? word register [15:0] 0x4ea C 0x4eb 0x4ea 0x4eb ts7_smpl1_sh 0x0000 timestamp unit 7 input sample time (1 st ) in second s high ? word register [31:16] 0x4ec C 0x4ed 0x4ec 0x4ed ts7_smpl1_sub_ns 0x0000 timestamp unit 7 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x4ee C 0x4f3 0x4ee 0x4f3 reserved (6 ? byte s dont c are none 0x4f4 C 0x4f5 0x4f4 0x4f5 ts7_smpl2_nsl 0x0000 timestamp unit 7 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x4f6 C 0x4f7 0x4f6 0x4f7 ts7_smpl2_nsh 0x0000 timestamp unit 7 input sample time (2nd) in nanosecond s high ? word register [29:16] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 113 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x4f8 C 0x4f9 0x4f8 0x4f9 ts7_smp2_sl 0x0000 timestamp unit 7 input sample time (2nd) in second s low ? word register [15:0] 0x4fa C 0x4fb 0x4fa 0x4fb ts7_smpl2_sh 0x0000 timestamp unit 7 input sample time (2nd) in second s high ? word register [31:16] 0x4fc C 0x4fd 0x4fc 0x4fd ts7_smpl2_sub_ns 0x0000 timestamp unit 7 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x4fe C 0x4ff 0x4fe 0x4ff reserved dont c are none 0x500 C 0x501 0x500 0x501 ts8_status 0x0000 timestamp input unit 8 status register 0x502 C 0x503 0x502 0x503 ts8_cfg 0x0000 timestamp input unit 8 configuration/control register 0x504 C 0x505 0x504 0x505 ts8_smpl1_nsl 0x0000 timestamp unit 8 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x506 C 0x507 0x506 0x507 ts8_smpl1_nsh 0x0000 timestamp unit 8 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x508 C 0x509 0x508 0x509 ts8_smpl1_sl 0x0000 timestamp unit 8 input sample time (1 st ) in second s low ? word register [15:0] 0x50a C 0x50b 0x50a 0x50b ts8_smpl1_sh 0x0000 timestamp unit 8 input sample time (1 st ) in second s high ? word register [31:16] 0x50c C 0x50d 0x50c 0x50d ts8_smpl1_sub_ns 0x0000 timestamp unit 8 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x50e C 0x513 0x50e 0x513 reserved (6 ? byte s) dont c are none 0x514 C 0x515 0x514 0x515 ts8_smpl2_nsl 0x0000 timestamp unit 8 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x516 C 0x517 0x516 0x517 ts8_smpl2_nsh 0x0000 timestamp unit 8 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x518 C 0x519 0x518 0x519 ts8_smp2_sl 0x0000 timestamp unit 8 input sample time (2nd) in second s low ? word register [15:0] 0x51a C 0x51b 0x51a 0x51b ts8_smpl2_sh 0x0000 timestamp unit 8 input sample time (2nd) in second s high ? word register [31:16] 0x51c C 0x51d 0x51c 0x51d ts8_smpl2_sub_ns 0x0000 timestamp unit 8 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x51e C 0x51f 0x51e 0x51f reserved dont c are none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 114 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 u nits, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x520 C 0x521 0x520 0x521 ts9_status 0x0000 timestamp input unit 9 status register 0x522 C 0x523 0x522 0x523 ts9_cfg 0x0000 timestamp input unit 9 configuration/control register 0x524 C 0x525 0x524 0x525 ts9_smpl1_nsl 0x0000 timestamp unit 9 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x526 C 0x527 0x526 0x527 ts9_smpl1_nsh 0x0000 timestamp unit 9 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x528 C 0x529 0x528 0x529 ts9_smpl1_sl 0x0000 timestamp unit 9 input sample time (1 st ) in second s low ? word register [15:0] 0x52a C 0x52b 0x52a 0x52b ts9_smpl1_sh 0x0000 timestamp unit 9 input sample time (1 st ) in second s high ? word register [31:16] 0x52c C 0x52d 0x52c 0x52d ts9_smpl1_sub_ns 0x0000 timestamp unit 9 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x52e C 0x533 0x52e 0x533 reserved (6 ? byte s) dont c are none 0x534 C 0x535 0x534 0x535 ts9_smpl2_nsl 0x0000 timestamp unit 9 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x536 C 0x537 0x536 0x537 ts9_smpl2_nsh 0x0000 timestamp unit 9 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x538 C 0x539 0x538 0x539 ts9_smp2_sl 0x0000 timestamp unit 9 input sample time (2nd) in second s low ? word register [15:0] 0x53a C 0x53b 0x53a 0x53b ts9_smpl2_sh 0x0000 timestamp unit 9 input sample time (2nd) in second s high ? word register [31:16] 0x53c C 0x53d 0x53c 0x53d ts9_smpl2_sub_ns 0x0000 timestamp unit 9 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x53e C 0x53f 0x53e 0x53f reserved dont c are none 0x540 C 0x541 0x540 0x541 ts10_status 0x0000 timestamp input unit 10 status register 0x542 C 0x543 0x542 0x543 ts10_cfg 0x0000 timestamp input unit 10 configuration/control register 0x544 C 0x545 0x544 0x545 ts10_smpl1_nsl 0x0000 timestamp unit 10 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x546 C 0x547 0x546 0x547 ts10_smpl1_nsh 0x0000 timestamp unit 10 input sample time (1 st ) in nanosecond s high ? word register [29:16] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 115 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x548 C 0x549 0x548 0x549 ts10_smpl1_sl 0x0000 timestamp unit 10 input sample time (1 st ) in second s low ? word register [15:0] 0x54a C 0x54b 0x54a 0x54b ts10_smpl1_sh 0x0000 timestamp unit 10 input sample time (1 st ) in second s high ? word register [31:16] 0x54c C 0x54d 0x54c 0x54d ts10_smpl1_sub_ns 0x0000 timestamp unit 10 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x54e C 0x553 0x54e 0x553 reserved (6 ? byte s) dont c are none 0x554 C 0x555 0x554 0x555 ts10_smpl2_nsl 0x0000 timestamp unit 10 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x556 C 0x557 0x556 0x557 ts10_smpl2_nsh 0x0000 timestamp unit 10 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x558 C 0x559 0x558 0x559 ts10_smp2_sl 0x0000 timestamp unit 10 input sample time (2nd) in second s low ? word register [15:0] 0x55a C 0x55b 0x55a 0x55b ts10_smpl2_sh 0x0000 timestamp unit 10 input sample time (2nd) in second s high ? word register [31:16] 0x55c C 0x55d 0x55c 0x55d ts10_smpl2_sub_ns 0x0000 timestamp unit 10 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x55e C 0x55f 0x55e 0x55f reserved dont c are none 0x560 C 0x561 0x560 0x561 ts11_status 0x0000 timestamp input unit 11 status register 0x562 C 0x563 0x562 0x563 ts11_cfg 0x0000 timestamp input unit 11 configuration/control register 0x564 C 0x565 0x564 0x565 ts11_smpl1_nsl 0x0000 timestamp unit 11 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x566 C 0x567 0x566 0x567 ts11_smpl1_nsh 0x0000 timestamp unit 11 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x568 C 0x569 0x568 0x569 ts11_smpl1_sl 0x0000 timestamp unit 11 input sample time (1 st ) in second s low ? word register [15:0] 0x56a C 0x56b 0x56a 0x56b ts11_smpl1_sh 0x0000 timestamp unit 11 input sample time (1 st ) in second s high ? word register [31:16] 0x56c C 0x56d 0x56c 0x56d ts11_smpl1_sub_ns 0x0000 timestamp unit 11 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x56e C 0x573 0x56e 0x573 reserved (6 ? byte s) dont c are none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 116 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x574 C 0x575 0x574 0x575 ts11_smpl2_nsl 0x0000 timestamp unit 11 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x576 C 0x577 0x576 0x577 ts11_smpl2_nsh 0x0000 timestamp unit 11 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x578 C 0x579 0x578 0x579 ts11_smp2_sl 0x0000 timestamp unit 11 input sample time (2nd) in second s low ? word register [15:0] 0x57a C 0x57b 0x57a 0x57b ts11_smpl2_sh 0x0000 timestamp unit 11 input sample time (2nd) in second s high ? word register [31:16] 0x57c C 0x57d 0x57c 0x57d ts11_smpl2_sub_ns 0x0000 timestamp unit 11 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x57e C 0x57f 0x57e 0x57f reserved dont c are none 0x580 C 0x581 0x580 0x581 ts12_status 0x0000 timestamp input unit 12 status register 0x582 C 0x583 0x582 0x583 ts12_cfg 0x0000 timestamp input unit 12 configuration/control register 0x584 C 0x585 0x584 0x585 ts12_smpl1_nsl 0x0000 timestamp unit 12 input sample time (1 st ) in nanosecond s low ? word register [15:0] 0x586 C 0x587 0x586 0x587 ts12_smpl1_nsh 0x0000 timestamp unit 12 input sample time (1 st ) in nanosecond s high ? word register [29:16] 0x588 C 0x589 0x588 0x589 ts12_smpl1_sl 0x0000 timestamp unit 12 input sample time (1 st ) in second s low ? word register [15:0] 0x58a C 0x58b 0x58a 0x58b ts12_smpl1_sh 0x0000 timestamp unit 12 input sample time (1 st ) in second s high ? word register [31:16] 0x58c C 0x58d 0x58c 0x58d ts12_smpl1_sub_ns 0x0000 timestamp unit 12 input sample time (1 st ) in sub ? nanosecond s register [2:0] 0x58e C 0x593 0x58e 0x593 reserved (6 ? byte s) dont c are none 0x594 C 0x595 0x594 0x595 ts12_smpl2_nsl 0x0000 timestamp unit 12 input sample time (2nd) in nanosecond s low ? word register [15:0] 0x596 C 0x597 0x596 0x597 ts12_smpl2_nsh 0x0000 timestamp unit 12 input sample time (2nd) in nanosecond s high ? word register [29:16] 0x598 C 0x599 0x598 0x599 ts12_smp2_sl 0x0000 timestamp unit 12 input sample time (2nd) in second s low ? word register [15:0] 0x59a C 0x59b 0x59a 0x59b ts12_smpl2_sh 0x0000 timestamp unit 12 input sample time (2nd) in second s high ? word register [31:16] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 117 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x59c C 0x59d 0x59c 0x59d ts12_smpl2_sub_ns 0x0000 timestamp unit 12 input sample time (2nd) in sub ? nanosecond s register [2:0] 0x59e C 0x5a3 0x59e 0x5a3 reserved (6 ? byte s) dont c are none 0x5a4 C 0x5a5 0x5a4 0x5a5 ts12_smpl3_nsl 0x0000 timestamp unit 12 input sample time (3rd) in nanosecond s low ? word register [15:0] 0x5a6 C 0x5a7 0x5a6 0x5a7 ts12_smpl3_nsh 0x0000 timestamp unit 12 input sample time (3rd) in nanosecond s high ? word register [29:16] 0x5a8 C 0x5a9 0x5a8 0x5a9 ts12_smpl3_sl 0x0000 timestamp unit 12 input sample time (3rd) in second s l ow ? word register [15:0] 0x5aa C 0x5ab 0x5aa 0x5ab ts12_smpl3_sh 0x0000 timestamp unit 12 input sample time (3rd) in second s high ? word register [31:16] 0x5ac C 0x5ad 0x5ac 0x5ad ts12_smpl3_sub_ns 0x0000 timestamp unit 12 input sample time (3rd) in sub ? nanosecond s register [2:0] 0x5ae C 0x5b3 0x5ae 0x5b3 reserved (6 ? byte s) dont c are none 0x5b4 C 0x5b5 0x5b4 0x5b5 ts12_smpl4_nsl 0x0000 timestamp unit 12 input sample time (4th) in nanosecond s low ? word register [15:0] 0x5b6 C 0x5b7 0x5b6 0x5b7 ts12_smpl4_nsh 0x0000 timestamp unit 12 input sample time (4th) in nanosecond s high ? word register [29:16] 0x5b8 C 0x5b9 0x5b8 0x5b9 ts12_smpl4_sl 0x0000 timestamp unit 12 input sample time (4th) in second s low ? word register [15:0] 0x5ba C 0x5bb 0x5ba 0x5bb ts12_smpl4_sh 0x0000 timestamp unit 12 input sample time (4th) in second s high ? word register [31:16] 0x5bc C 0x5bd 0x5bc 0x5bd ts12_smpl4_sub_ns 0x0000 timestamp unit 12 input sample time (4th) in sub ? nanosecond s register [2:0] 0x5be C 0x5c3 0x5be 0x5c3 reserved (6 ? byte s) dont c are none 0x5c4 C 0x5c5 0x5c4 0x5c5 ts12_smpl5_nsl 0x0000 timestamp unit 12 input sample time (5th) in nanosecond s low ? word register [15:0] 0x5c6 C 0x5c7 0x5c6 0x5c7 ts12_smpl5_nsh 0x0000 timestamp unit 12 input sample time (5th) in nanosecond s high ? word register [29:16] 0x5c8 C 0x5c9 0x5c8 0x5c9 ts12_smpl5_sl 0x0000 timestamp unit 12 input sample time (5th) in second s low ? word register [15:0] 0x5ca C 0x5cb 0x5ca 0x5cb ts12_smpl5_sh 0x0000 timestamp unit 12 input sample time (5th) in second s high ? word register [31:16] 0x5cc C 0x5cd 0x5cc 0x5cd ts12_smpl5_sub_ns 0x0000 timestamp unit 12 input sample time (5th) in sub ? nanosecond s register [2:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 118 revision 1.0 internal i/o register space mapping for ptp event timestamp input (12 units, 0x400 C 0x5ff) (continued) i/o register offset location register name default value description 16 - bit 8- bit 0x5ce C 0x5d3 0x5ce 0x5d3 reserved (6 ? byte s) dont c are none 0x5d4 C 0x5d5 0x5d4 0x5d5 ts12_smpl6_nsl 0x0000 timestamp unit 12 input sample time (6th) in nanosecond s low ? word register [15:0] 0x5d6 C 0x5d7 0x5d6 0x5d7 ts12_smpl6_nsh 0x0000 timestamp unit 12 input sample time (6th) in nanosecond s high ? word register [29:16] 0x5d8 C 0x5d9 0x5d8 0x5d9 ts12_smpl6_sl 0x0000 timestamp unit 12 input sample time (6th) in second s low ? word register [15:0] 0x5da C 0x5db 0x5da 0x5db ts12_smpl6_sh 0x0000 timestamp unit 12 input sample time (6th) in second s high ? word register [31:16] 0x5dc C 0x5dd 0x5dc 0x5dd ts12_smpl6_sub_ns 0x0000 timestamp unit 12 input sample time (6th) in sub ? nanosecond s register [2:0] 0x5de C 0x5e3 0x5de 0x5e3 reserved (6 ? byte s) dont c are none 0x5e4 C 0x5e5 0x5e4 0x5e5 ts12_smpl7_nsl 0x0000 timestamp unit 12 input sample time (7th) in nanosecond s low ? word register [15:0] 0x5e6 C 0x5e7 0x5e6 0x5e7 ts12_smpl7_nsh 0x0000 timestamp unit 12 input sample time (7th) in nanosecond s high ? word register [29:16] 0x5e8 C 0x5e9 0x5e8 0x5e9 ts12_smpl7_sl 0x0000 timestamp unit 12 input sample time (7th) in second s low ? word register [15:0] 0x5ea C 0x5eb 0x5ea 0x5eb ts12_smpl7_sh 0x0000 timestamp unit 12 input sample time (7th) in second s high ? word register [31:16] 0x5ec C 0x5ed 0x5ec 0x5ed ts12_smpl7_sub_ns 0x0000 timestamp unit 12 input sample time (7th) in sub ? nanosecond s register [2:0] 0x5ee C 0x5f3 0x5ee 0x5f3 reserved (6 ? byte s) dont c are none 0x5f4 C 0x5f5 0x5f4 0x5f5 ts12_smpl8_nsl 0x0000 timestamp unit 12 input sample time (8th) in nanosecond s low ? word register [15:0] 0x5f6 C 0x5f7 0x5f6 0x5f7 ts12_smpl8_nsh 0x0000 timestamp unit 12 input sample time (8th) in nanosecond s high ? word register [29:16] 0x5f8 C 0x5f9 0x5f8 0x5f9 ts12_smpl8_sl 0x0000 timestamp unit 12 input sample time (8th) in second s low ? word register [15:0] 0x5fa C 0x5fb 0x5fa 0x5fb ts12_smpl8_sh 0x0000 timestamp unit 12 i nput sample time (8th) in second s high ? word register [31:16] 0x5fc C 0x5fd 0x5fc 0x5fd ts12_smpl8_sub_ns 0x0000 timestamp unit 12 input sample time (8th) in sub ? nanosecond s register [2:0] 0x5fe C 0x5ff 0x5fe 0x5ff reserved dont c are none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 119 revision 1.0 internal i/o register space mapping for ptp 1588 clock and g lobal control (0x600 C 0x7ff) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x600 C 0x601 0x600 0x601 ptp_clk_ctl 0x000 2 ptp clock control register [6:0] 0x602 C 0x603 0x602 0x603 reserved (2?bytes) dont c are none 0x604 C 0x605 0x604 0x605 ptp_rtc_nsl 0x0000 ptp real time clock in nanosecond s low ? word register [15:0] 0x606 C 0x607 0x606 0x607 ptp_rtc_nsh 0x0000 ptp real time clock in nanosecond s high ? word register [31:16] 0x608 C 0x609 0x608 0x609 ptp_rtc_sl 0x0000 ptp real time clock in second s low ? word register [15:0] 0x60a C 0x60b 0x60a 0x60b ptp_rtc_sh 0x0000 ptp real time clock in second s high ? word register [31:16] 0x60c C 0x60d 0x60c 0x60d ptp_rtc_phase 0x0000 ptp real time clock in phase register [2:0] 0x60e C 0x60f 0x60e 0x60f reserved (2?bytes) dont c are none 0x610 C 0x611 0x610 0x611 ptp_sns_rate_l 0x0000 ptp sub ? n anosecond rate low ? word register [15:0] 0x612 C 0x613 0x612 0x613 ptp_sns_rate_h 0x0000 ptp sub ? nanosecond rate high ? word [29:16] and configuration register 0x614 C 0x615 0x614 0x615 ptp_temp_adj_dura_l 0x0000 ptp temporary adjustment mode duration low ? word register [15:0] 0x616 C 0x617 0x616 0x617 ptp_temp_adj_dura_h 0x0000 ptp temporary adjustment mode duration high ? word register [31:16] 0x618 C 0x61f 0x618 0x61f reserved (8 ? byte s) dont c are none 0x620 C 0x621 0x620 0x621 ptp_msg_cfg_1 0x0 059 ptp message configuration 1 register [7:0] 0x622 C 0x623 0x622 0x623 ptp_msg_cfg_2 0x0404 ptp mes sage configuration 2 register [10 :0] 0x624 C 0x625 0x624 0x625 ptp_domain_ver 0x0 2 00 ptp domain and version register [11:0] 0x626 C 0x63f 0x626 0x63f reserved (26 ? byte s) dont c are none 0x640 C 0x641 0x640 0x641 ptp_p1_rx_ latency 0x0 19f ptp port 1 receive latency register [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 120 revision 1.0 internal i/o register space mapping for ptp 1588 clock and g lobal control (0x600 C 0x7ff) (continued) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x642 C 0x643 0x642 0x643 ptp_p1_tx_ latency 0x002d ptp port 1 transmit latency register [15:0] 0x644 C 0x645 0x644 0x645 ptp_p1_asym_cor 0x0000 ptp port 1 asymmetry correction register [15:0] 0x646 C 0x647 0x646 0x647 ptp_p1_link_dly 0x0000 ptp port 1 link delay register [15:0] 0x648 C 0x649 0x648 0x649 p1_xdly_req_tsl 0x0000 ptp port 1 egress timestamp low ? word for pdelay_req and delay_req frames register [15:0] 0x64a C 0x64b 0x64a 0x64b p1_xdly_req_tsh 0x0000 ptp port 1 egress timestamp high ? word for pdelay_req and delay_req frames register [31:16] 0x64c C 0x64d 0x64c 0x64d p1_sync_tsl 0x0000 ptp port 1 egress timestamp low ? word for sync frame register [15:0] 0x64e C 0x64f 0x64e 0x64f p1_sync_tsh 0x0000 ptp port 1 egress timestamp high ? word for sync frame register [31:16] 0x650 C 0x651 0x650 0x651 p1_pdly_resp_tsl 0x0000 ptp port 1 egress timestamp low ? word for pdelay_resp frame register [15:0] 0x652 C 0x653 0x652 0x653 p1_pdly_resp_tsh 0x0000 ptp port 1 egress timestamp high ? word for pdelay_resp frame register [31:16] 0x654 C 0x65f 0x654 0x65f reserved (12 ? byte s) dont c are none 0x660 C 0x661 0x660 0x661 ptp_p2_rx_latency 0x0 19f ptp port 2 receive latency register [15:0] 0x662 C 0x663 0x662 0x663 ptp_p2_tx_ latency 0x002d ptp port 2 transmit latency register [15:0] 0x664 C 0x665 0x664 0x665 ptp_p2_asym_cor 0x0000 ptp port 2 asymmetry correction register [15:0] 0x666 C 0x667 0x666 0x667 ptp_p2_link_dly 0x0000 ptp port 2 link delay register [15:0] 0x668 C 0x669 0x668 0x669 p2_xdly_req_tsl 0x0000 ptp port 2 egress timestamp low ? word for pdelay_req and delay_req frames register [15:0] 0x66a C 0x66b 0x66a 0x66b p2_xdly_req_tsh 0x0000 ptp port 2 egress timestamp high ? word for pdelay_req and delay_req frames register [31:16] 0x66c C 0x66d 0x66c 0x66d p2_sync_tsl 0x0000 ptp port 2 egress timestamp low ? word for sync frame register [15:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 121 revision 1.0 internal i/o register space mapping for ptp 1588 clock and g lobal control (0x600 C 0x7ff) (continued) i/o register offset location register name default value description 16 ? bit 8 ? bit 0x66e C 0x66f 0x66e 0x66f p2_sync_tsh 0x0000 ptp port 2 egress timestamp high ? word for sync frame register [31:16] 0x670 C 0x671 0x670 0x671 p2_pdly_resp_tsl 0x0000 ptp port 2 egress timestamp low ? word for pdelay_resp frame register [15:0] 0x672 C 0x673 0x672 0x673 p2_pdly_resp_tsh 0x0000 ptp port 2 egress timestamp high ? word for pdelay_resp frame register [31:16] 0x674 C 0x67f 0x674 0x67f reserved (12 ? byte s) dont c are none 0x680 C 0x681 0x680 0x681 gpio_monitor 0x0000 ptp gpio monitor register [11 :0] 0x682 C 0x683 0x682 0x683 gpio_oen 0x0000 pt p gpio output enable register [11 :0] 0x684 C 0x687 0x686 0x687 reserved (4 ? byte s) dont c are none 0x688 C 0x689 0x688 0x689 ptp_trig_is 0x0000 ptp trigger unit interrupt status register 0x68a C 0x68b 0x68a 0x68b ptp_trig_ie 0x0000 ptp trigger unit interrupt enable register 0x68c C 0x68d 0x68c 0x68d ptp_ts_is 0x0000 ptp timestamp unit interrupt status register 0x68e C 0x68f 0x68e 0x68f ptp_ts_ie 0x0000 ptp timestamp unit interrupt enable register 0x690 C 0x733 0x690 0x733 reserved (164? b ytes ) dont c are none 0x734 C 0x735 0x734 0x735 dsp_cntrl_6 0x3020 dsp control 6 register 0x736 C 0x747 0x736 0x747 reserved (18? bytes ) dont c are none 0x748 C 0x749 0x748 0x749 ana_cntrl_1 0x0000 analog control 1 register 0x74a C 0x74b 0x74a 0x74b reserved (2- bytes ) dont care none 0x74c C 0x74d 0x74c 0x74d ana_cntrl_3 0x0000 analog control 3 register 0x74e C 0x7ff 0x74e 0x7ff reserved ( 178 - bytes ) dont care none downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 122 revision 1.0 register bit definitions the section provides details of the bit definitions for the registers summ arized in the previous section. writing to a bit or register defined as reserved could potentially cause unpredictable results. if it is necessar y to write to registers which contain both writable and reserved bits in the same register, the user should first read back the reserved bits ( ro or rw), then or the desired settable bits with the value read and write back the ored value back to the register. bit type definition: ro = re ad only wo = write only rw = read/write sc = self? clear w1c = write 1 to clear (write a 1 to clear this bit) internal i/o register mapping for switch control and configuratio n (0x000 ? 0x0ff) chip id and enable register (0x00 ? 0x001 ) : cider this regi ster contains the chip id and switch - enable control. bit default value r/w description 15?8 0x84 ro family id chip family id. 7?4 0x3 ro chip id 0x3 is assigned to the ksz8462. 3?1 001 ro revision id chip revision id. 0 1 rw start switch 1 = start the chip. 0 = switch is disabled. switch global control register 1 (0x002 ? 0x003): sgcr1 this register contains global control bits for the switch function. bit default r/w description 15 0 rw pass all frames 1 = switch all packets including bad ones. used solely for debugging purposes. works in conjunction with sniffer mode only. 14 0 rw receive 2000 byte packet length enable 1 = enables the receipt of packets up to and including 2000 bytes in length. 0 = discards the received packets if their length is greater than 2000 bytes. 13 1 rw ieee 802.3x transmit direction flow control enable 1 = enables transmit direction flow control feature. 0 = disable transmit direction flow control feature. the switch will not generate any flow control packets. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 123 revision 1.0 switch global control register 1 (0x002 ? 0x003): sgcr1 (continued) bit default r/w description 12 1 rw ieee 802.3x receive direction flow control enable 1 = enables receive direction flow control feature. 0 = disable receive direction flow control feature. the switch will not react to any received flow control packets. 11 0 rw frame length field check 1 = enable check ing frame length field in the ieee packets. if the actual length does not match, the packet will be dropped (for length/type field < 1500). 0 = disable check ing frame length field in the ieee packets. 10 1 rw aging enable 1 = enable ag ing function in the chip. 0 = disable aging function in the chip. 9 0 rw fast age enable 1 = turn on fast aging (800 us). 8 0 rw aggressive back?off enable 1 = enable more aggressive back - off algorithm in half?duplex mode to enhance performance. this is not an ieee standard. 7 ?6 01 rw reserved 5 0 rw enable flow control when exceeding ingress limit 1 = flow control frame will be sent to link partner when exceeding the ingress rate limit. 0 = frame will be dropped when exceeding the ingress rate limit 4 1 rw receive 2k byte packets enable 1 = enable packet length up to 2k bytes. whi le set, sgcr2 bits[2,1] will have no effect. 0 = discard packet if packet length is greater than 2000 bytes. 3 0 rw pass flow control packet 1 = switch will not filter 802.1x flow control packets. 2 ? 1 00 rw reserved 0 0 rw link change age 1 = link change from link to no link will cause fast aging (<800us) to age address table faster. after an age cycle is complete, the age logic will return to normal (300 + 75 seconds). note: if any port is unplugged, all addresses will be autom atically aged out. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 124 revision 1.0 switch global control register 2 (0x004 C 0x005): sgcr2 this register contains global control bits for the switch function. bit default r/w description 15 0 rw 802.1q vlan enable 1 = 802.1q vlan mode is turned on. vlan table must be set up before the operation. 0 = 802.1q vlan is disabled. 14 0 rw igmp snoop enable 1 = igmp snoop is enabled. 0 = igmp snoop is disabled. 13 0 rw ipv6 mld snooping enable 1 = enable ipv6 mld snooping. 12 0 rw ipv6 mld snooping option 1 = enable ipv6 mld snooping option. 11 ?9 000 rw reserved 8 0 rw sniff mode select 1 = performs rx and tx sniff (both the source port and destination port need to match). 0 = performs rx or tx sniff (either the source port or destination port needs to match). this is the mode used to implement rx only sniff. 7 1 rw unicast port?vlan mismatch discard 1 = no packets can cross the vlan boundary. 0 = unicast packets (excluding unknown/multicast/broadcast) can cross the vlan boundary. 6 1 rw multicast storm protection disable 1 = broadcast storm protection does not include multicast packets. only da = ff - ff - ff - ff - ff - ff packets are regulated. 0 = broadcast storm protection includes da = ff - ff - ff - ff - ff - ff and da[40] = 1 packets. 5 1 rw back pressure mode 1 = carrier sense?based b ack pressure is selected. 0 = collision?based b ack p ressure is selected. 4 1 rw flow control a nd back pressure fair mode 1 = fair mode is selected. in this mode, if a flow control port and a non? flow control port talk to the same destination port, packets from the non?flow control port may be dropped. this prevents the flow control port from being flow controlled for an extended period of time. 0 = in this mode, if a flow control port and a non?flow c ontrol port talk to the same destination port, the flow control port is flow controlled. this may not be fair to th e flow control port. 3 0 rw no excessive collision drop 1 = the switch does not drop packets when 16 or more collisions occur. 0 = the switch drops packets when 16 or more collisions occur. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 125 revision 1.0 switch global control register 2 (0x004 C 0x005): sgcr2 (continued) bit default r/w description 2 0 rw huge packet support 1 = accepts packet sizes up to 1916 bytes (inclusive). this bit setting overrides setting from bit 1 of the same register. 0 = the max packet size is determined by bit [1] of this register. 1 0 rw legal maximum packet size check enable 1 = 1522 bytes for tagged packets, 1518 bytes for untagged packets. any packets larger than the specified value are dropped. 0 = accepts packet sizes up to 1536 bytes (inclusive). 0 0 rw priority buffer reserve 1 = each port is pre?allocated 48 buffe rs, used exclusively for high priority (q3, q2, and q1 ) packets. effective only when the multiple queue feature is turned on. 0 = each port is pre?allocated 48 buffers used for all priority packets (q3, q2 , q1 , and q0). switch global control register 3 (0x006 C 0x007): sgcr3 this register contains global control bits for the switch function. bit default r/w description 15?8 0x63 rw broadcast storm protection rate bit [7:0] these bits, along with sgcr3[ 2:0], determine how many 64?byte blocks of packet data are allowed on an input port in a preset period. the period is 67ms for 100bt or 670 ms for 10bt. the default is 1%. 7 0 ro reserved 6 0 rw switch host port in half?duplex mode 1 = enable host port in terface half?duplex mode. 0 = enable host port interface full?duplex mode. 5 1 rw switch host port flow control enable 1 = enable full?duplex flow control on switch host port. 0 = disable full?duplex flow control on switch host port 4 0 rw switch mii 10bt 1 = the switch is in 10 mbps mode. 0 = t he switch is in 100mbps mode. 3 0 rw null vid replacement 1 = replaces null vid with port vid (12 bits). 0 = no replacement for null vid. 2?0 000 rw broadcast storm protection rate bit [10:8] these bits, along with sgcr3[15:8] determine how many 64?byte blocks of packet data are allowed on an input port in a preset period. the period is 67ms for 100bt or 670 ms for 10bt. the default is 1%. broadcast storm protectio n rate: 148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx. 0x63) 0x008 C 0x00 b : reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 126 revision 1.0 switch global control register 6 (0x00c C 0x00d): sgcr6 this register contains global control bits for the switch function. bit default r/w description 15 ? 14 11 r/w tag_0x7 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a value of 0x7. 13 ? 12 11 r/w tag_0x6 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a value of 0x6. 11 ? 10 10 r/w tag_0x5 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a value of 0x5. 9 ? 8 10 r/w tag_0x4 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a va lue of 0x4. 7 ? 6 01 r/w tag_0x3 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a value of 0x3. 5 ? 4 01 r/w tag_0x2 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a value of 0x2. 3 ? 2 00 r/w tag_0x1 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a value of 0x1. 1 ? 0 00 r/w tag_0x0 ieee 802.1p mapping. the value in this field is used as the frames priority when its vlan tag has a value of 0x0. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 127 revision 1.0 switch global control register 7 (0x00e C 0x00f): sgcr7 this register contains global control bits for the switch function. bit default r/ w description 15? 10 0x02 r/w reserved 9?8 00 r/w port led mode when read, these two bits provide the current setting of the led display mode for p1/2led1 and p1/2led0 as defined as below. reg. 0x06c C 0x06d, bits[ 14:12] determine if this automatic functionality is utilized or if the port 1 leds are controlled by the local processor. reg. 0x084 C 0x085, bits[ 14:12] determine if this automatic functionality is utilized or if the port 2 leds are controlled by the host processor. led mode p1/2led1 p1/2led0 00 speed link & activity 01 activity link 10 full duplex link & activity 11 full duplex link 7 0 r/w unknown default port enable send packets with unknown destination address to specified ports in bits[ 2:0]. 1 = enable to send unknown da packet 6?5 01 or 10 r/w driver strength selection these two bits determine the drive strength of all i/o pins except for the following category of pi ns: led pins, gpio pins, intrn, and rstn. 00 = 4ma. 01 = 8ma. (default when vdd_io is 3.3v or 2.5v) 10 = 12ma. (default when vdd_io is 1.8v) 11 = 16ma. 4?3 00 r/w reserved 2?0 111 r/w unknown packet default port(s) specify which ports to send packets with unknown destination addresses. feature is enabled by bit [7]. bit[2] = for port 3 (host port) bit[1] = for port 2 bit[0] = for port 1 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 128 revision 1.0 mac address register 1 (0x010 C 0x011): macar1 this register contains the two msbs of the mac address for the switch function. this mac address is used for sending pause frames. bit default r/w description 15?0 0x0010 rw maca[47:32] specifies mac address 1 for sending pause frame. mac address register 2 (0x012 C 0x013): macar2 this register contains the mac address for the switch function. this mac address is used for sending pause frames. bit default r/w description 15?0 0xa1ff rw maca[31:16] specifies mac address 2 for sending pause frame. mac address register 3 (0x014 C 0x015): macar3 this register contains the two lsbs of the mac address for the switch function. this mac address is used for sending pause frames. bit default r/w description 15?0 0xffff rw maca[15:0] specifies mac address 3 for sending pause frame. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 129 revision 1.0 type -of-service (tos) priority control registers tos priority control register 1 (0x016 C 0x017): tosr1 the ipv4/ipv6 type - of - service ( tos ) priority control registers are used to define a 2 - bit priority to each of the 64 possible values in the 6 - bit differentiated services code point (dscp) field in the ip header of ingress frames. this register contains the tos priority control bits for the switch function. bit default r/w description 15?14 00 rw dscp[15:14] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x1c. 13?12 00 r/w dscp[13:12] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x18. 11?10 00 r/w dscp[11:10] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x14. 9?8 00 r/w dscp[9:8] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x10. 7?6 00 r/w dscp[7:6] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x0c. 5?4 00 r/w dscp[5:4] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class va lue are 0x08. 3?2 00 r/w dscp[3:2] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x04. 1?0 00 r/w dscp[1:0] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x00. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 130 revision 1.0 tos priority control register 2 (0x018 C 0x019): tosr2 this register contains the tos priority control bits for the switch function. bit default r/w description 15 ? 14 00 rw dscp[31:30] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x3c. 13 ? 12 00 r/w dscp[29:28] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x38. 11 ? 10 00 r/w dscp[27:26] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x34. 9 ? 8 00 r/w dscp[25:24] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x30. 7 ? 6 00 r/w dscp[23:22] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x2c. 5 ? 4 00 r/w dscp[21:20] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x28. 3 ? 2 00 r/w dscp[19:18] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x24. 1 ? 0 00 r/w dscp[17:16] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x20. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 131 revision 1.0 to s priority control register 3 (0x01a C 0x01b): tosr3 this register contains the tos priority control bits for the switch function. bit default r/w description 15 ? 14 00 rw dscp [47:46] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x5c. 13 ? 12 00 r/w dscp[45:44] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x58. 11 ? 10 00 r/w dscp[43:42] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x54. 9 ? 8 00 r/w dscp[41:40] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x50. 7 ? 6 00 r/w dscp[39:38] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x4c. 5 ? 4 00 r/w dscp[37:36] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x48. 3 ? 2 00 r/w dscp[35:34] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x44. 1 ? 0 00 r/w dscp[33:32] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x40. tos priority control register 4 (0x01c C 0x1d): tosr4 this register contains the tos priority control bits for the switch function. bit default r/w description 15 ? 14 00 rw dscp[63:62] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x7c. 13 ? 12 00 r/w dscp[61:60] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x78. 11 ? 10 00 r/w dscp[59:58] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x74. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 132 revision 1.0 tos priority control register 4 (0x01c C 0x1d): tosr4 (continued) bit default r/w description 9 ? 8 00 r/w dscp[57:56] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x70. 7 ? 6 00 r/w dscp[55:54] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x6c. 5 ? 4 00 r/w dscp[53:52] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x68. 3 ? 2 00 r/w dscp[51:50] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x64. 1 ? 0 00 r/w dscp[49:48] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x60. tos priority control register 5 (0x01e C 0x1f): tosr5 this register contains the tos priority control bits for the switch function. bit default r/w description 15 ? 14 00 rw dscp[79:78] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x9c. 13 ? 12 00 r/w dscp[77:76] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x98. 11 ? 10 00 r/w dscp[75:74] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x94. 9 ? 8 00 r/w dscp[73:72] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x90. 7 ? 6 00 r/w dscp[71:70] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x8c. 5 ? 4 00 r/w dscp[69:68] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x88. 3 ? 2 00 r/w dscp[67:66] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x84. 1 ? 0 00 r/w dscp[65:64] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0x80. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 133 revision 1.0 tos priority control register 6 (0x020 C 0x021): tosr6 this register contains the tos priority control bits for the switch function. bit default r/w description 15 ? 14 00 rw dscp[95:94] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value is 0xbc. 13 ? 12 00 r/w dscp[93:92] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xb8. 11 ? 10 00 r/w dscp[91:90] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xb4. 9 ? 8 00 r/w dscp[89:88] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xb0. 7 ? 6 00 r/w dscp[87:86] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xac. 5 ? 4 00 r/w dscp[85:84] the value in this field is used as the frames prior it y when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xa8. 3 ? 2 00 r/w dscp[83:82] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xa4. 1 ? 0 00 r/w dscp[81:80] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xa0. tos priority control register 7 (0x022 C 0x023): tosr7 this register contains the tos priority control bits for the switch function. bit default r/w description 15 ? 14 00 rw dscp[111:110] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xdc. 13 ? 12 00 r/w dscp[109:108] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xd8. 11 ? 10 00 r/w dscp[107:106] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xd4. 9 ? 8 00 r/w dscp[105:104] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xd0. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 134 revision 1.0 tos priority control register 7 (0x022 C 0x023 ): tosr7 (continued) bit default r/w description 7 ? 6 00 r/w dscp[103:102] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xcc. 5 ? 4 00 r/w dscp[101:100] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xc8. 3 ? 2 00 r/w dscp[99:98] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xc4. 1 ? 0 00 r/w dscp[97:96] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xc0. tos priority control register 8 (0x024 C 0x025): tosr8 this register contains the tos priority control bits for the switch function. bit default r/w description 15 ? 14 00 rw dscp[127:126] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xfc 13 ? 12 00 r/w dscp[125:124] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xf8. 11 ? 10 00 r/w dscp[123:122] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xf4. 9 ? 8 00 r/w dscp[121:120] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xf0. 7 ? 6 00 r/w dscp[119:118] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xec. 5 ? 4 00 r/w dscp[117:116] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic clas s value are 0xe8. 3 ? 2 00 r/w dscp[115:114] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xe4. 1 ? 0 00 r/w dscp[113:112] the value in this field is used as the frames priority when bits[ 7:2] of the ip tos/diffserv/traffic class value are 0xe0. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 135 revision 1.0 indirect access data registers indirect access data register 1 (0x026 C 0x027): iadr1 this register is used to indirectly read or write the data in the management information base (mib) counters , static mac address table , dynamic mac address table , or the vlan table . bit default r/w description 15?8 0x00 ro reserved 7 0 ro cpu read status only for dynamic and statistics counter reads. 1 = read is still in progress. 0 = read has completed. 6?3 0x0 ro reserved 2?0 000 ro indirect data [66:64] bits [66:64] of indirect data. indirect access data register 2 (0x028 C 0x029): iadr2 this register is used to indirectly read or write the data in the management information base (mib) counters , static mac address table , dynamic mac address table , or the vlan table .. bit default r/w description 15?0 0x0000 rw indirect data [47:32] bits [47:32] of indirect data. indirect access data register 3 (0x02a C 0x02b): iadr3 this register is used to indirectly read or write the data in the management information base (mib) counters , static mac address table , dynamic mac address table , or the vlan table . bit default r/w description 15?0 0x0000 rw indirect data [63:48] bits [63:48] of indirect data. indirect access data register 4 (0x02c C 0x02d): iadr4 this register is used to indirectly read or write the data in the management information base (mib) counters , static mac address table , dynamic mac address table , or the vlan table . bit default r/w description 15?0 0x0000 rw indirect data [15:0] bits [15:0] of indirect data. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 136 revision 1.0 indirect access data register 5 (0x02e C 0x02f): iadr5 this register is used to indirectly read or write the data in the management information base (mib) counters , static mac address table , dynamic mac address table , or the vlan table . bit default r/w description 15?0 0x0000 rw indirect data [31:16] bits [31:16] of indirect data. indirect access control register (0x030 C 0x031): iacr this register is used to indirectly read or write the data in the management information base (mib) counters , static mac address table , dynamic mac address table , or the vlan table . writing to iacr triggers a command. read or write access is determined by r egister bit [ 12 ]. bit default r/w description 15?13 000 rw reserved 12 0 rw read or write access selection 1 = read cycle. 0 = write cycle. 11?10 00 rw table select 00 = static mac address table selected. 01 = vlan table selected. 10 = dynamic mac address table selected. 11 = mib counter selected. 9?0 0x000 rw indirect address [9:0] bits [9:0] of indirect address. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 137 revision 1.0 power management control and wake-up event status power management control and wake ?u p event status (0x032 C 0x033): pmctrl this register controls the power management mode and provides wake - up event status. bit default r/w description 15?6 0x000 ro reserved 5 0 rw (w1c) wake?up frame detect status 1 = a wake?up frame has been detected at the host qmu (w rite a 1 to clear ). 0 = no wake - up frame has been detected . 4 0 rw (w1c) magic packet detect status 1 = a magic packet has been detected at either port 1 or port 2 (w rite a 1 to clear ). 0 = n o magic packet has been detected . 3 0 rw (w1c) link - up detect status 1 = link -up has been detected at either port 1 or port 2 (w rite a 1 to clear ). 0 = n o l ink - up has been detected . 2 0 rw (w1c) energy detect status 1 = energy is detected at either port 1 or port 2 (w rite a 1 to clear ). 0 = no energy is detected . 1 ? 0 00 rw power management mode these two bits are used to control device power management mode. 00 = normal mode. 01 = energy d etect mode. 10 = global soft power - down mode. 11 = reserved . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 138 revision 1.0 power management event enable register (0x034 C 0x035): pmee this register contains the power management event enable control bits. bit default r/w description 15?5 0x000 rw reserved 4 0 rw pme polarity: 1 = the pme pin is active high. 0 = the pme pin is active low. 3 0 rw pme waked up by wake?up frame enable 1 = the pme pin will be asserted when a wake?up frame is detected. 0 = pme wont be asserted by the wake?up frame detection 2 0 rw pme waked up by magic packet enable 1 = the pme pin will be asserted when a magic packet is detected. 0 = pme wont be asserted by the magic packet detection 1 0 rw pme waked up by link - up enable 1 = the pme pin will be asserted when a link - up is detected at port 1 or port 2. 0 = pme wont be asserted by the link - up detection 0 0 rw pme waked up by energy detect enable 1 = the pme pin will be asserted when energy on line is detected at port 1 or port 2. 0 = pme wont be asserted by the energy detection. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 139 revision 1.0 go sleep time and clock tree power-down control registers go sleep time register (0x036 C 0x037): gst this register contains the value which is used to control the minimu m go?sleep time period when the device transitions from normal power state to low power state in energy detect mode. bit default r/w description 15?8 0x00 ro reserved 7?0 0x8e rw go sleep time this value is used to control the minimum period the no - energy event has to be detected consecutively before the device enters the low power state during energy detect mode. the unit is 20ms. the default go sleep time is around 3.0 seconds. clo ck tree power - down control register (0x038 C 0x039): ctpdc this register contains the power down control bits for all clocks. bit default r/w description 15 ? 5 0x00 0 ro reserved 4 0 rw reserved 3 0 rw switch clock auto shut down enable 1 = when no packet transfer is detected on the mii interface of all ports ( port 1 , port 2, and port 3 ) longer than the time specified in bit[1:0] of current register, the device will shut down the switch clock automatically. the switch clock will be w oken up automatically when the mii inte rface on any port becomes busy. 0 = s witch clock is always on. 2 0 rw cpu clock auto shut down enable 1 = when no packet transfer is detected on either the host interface or the mii interface of all ports ( port 1, port 2, and port 3) for a time period longer than the time specified in bit[1:0] of c urrent register, the device will shut down the cpu clock automatically. the cpu clock will be w oken up automatically when host activity is detect ed or the mii inte rface of any port becomes busy. 0 = cpu clock is always on. 1 ? 0 00 rw shutdown wait period these two bits specify the time for device to monitor host/mii activity continuously before it could shut down switch or cpu clock. 00 = 5.3 second . 01 = 1.6 second . 10 = 1 ms . 11 = 3.2 s. 0x03a C 0x0 4b: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 140 revision 1.0 phy and mii basic control registers phy 1 and mii basic control register (0x04c C 0x04d): p1mbcr this register contains media independent interface (mii) control bits for the switch port 1 function as defined in the ieee 802.3 specification. bit default r/w description bit is same a s: 15 0 ro reserved 14 0 rw far ? end loopback 1 = p erform loopback as follows: start: rxp2/rxm2 ( port 2) loop back: pmd/pma of port 1 s phy end: txp2/txm2 ( port 2) 0 = n ormal operation. b it [8] in p1cr4 13 1 rw force 100 bt 1 = f orce 100mbps if a uto - negotiation is disabled (bit [ 12 ]) 0 = f orce 10mbps if a uto - negotiation is disabled (bit [ 12 ]) b it [6 ] in p1cr4 12 1 rw auto- negotiation enable 1 = auto? negotiation enabled. 0 = auto? negotiation disabled. b it [7 ] in p1cr4 11 0 rw power ? down 1 = p ower ? down. 0 = n ormal operation. b it [ 11 ] in p1cr4 10 0 ro isolate not supported. 9 0 rw /sc restart a uto- negotiation 1 = r estart auto ? negotiation . 0 = n ormal operation. b it [ 13 ] in p1cr4 8 1 rw force full duplex 1 = f orce full duplex. 0 = f orce half duplex. applies only when auto - negotiation is disabled (bit [ 12 ]). it is always in half duplex if auto - negotiation is enabled but failed. b it [5 ] in p1cr4 7 0 ro collision t est not supported. 6 0 ro reserved . 5 1 r/w hp_mdi -x 1 = hp auto mdi ? x mode. 0 = micrel auto mdi ? x mode. b it [ 15 ] in p1sr downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 141 revision 1.0 phy 1 and mii basic control register (0x04c C 0x04d): p1mbcr (continued) bit default r/w description bit is same a s: 4 0 rw force mdi ? x 1 = f orce mdi ? x. 0 = n ormal operation. b it [9 ] in p1cr4 3 0 rw disable auto mdi ? x 1 = d isable a uto mdi ? x. 0 = n ormal operation. b it [ 10 ] in p1cr4 2 0 rw disable far ? end ? fault 1 = d isable far ? end ? fault detection. 0 = n ormal operation. for 100 base ? fx fiber mode operation. b it [ 12 ] in p1cr4 1 0 rw disable transmit 1 = d isable transmit. 0 = n ormal operation. b it [ 14 ] in p1cr4 0 0 rw reserved phy 1 and mii basic status register (0x04e C 0x04f): p1mbsr this register contains the media independent interface (mii) status bits for the switch port 1 function. bit default r/w description bit is same a s: 15 0 ro t4 capable 1 = 100base ? t4 capable. 0 = n ot 100base ? t4 capable. 14 1 ro 100 bt full capable 1 = 100base ? tx full ? duplex capable. 0 = n ot 100base ? tx full ? duplex capable. 13 1 ro 100 bt half capable 1 = 100base ? tx half ? duplex capable. 0 = n ot 100base ? tx half ? duplex capable. 12 1 ro 10 bt full capable 1 = 10base ? t full ? duplex capable. 0 = n ot 10base ? t full ? duplex capable. 11 1 ro 10 bt half capable 1 = 10base ? t half ? duplex capable. 0 = n ot 10base ? t half ? duplex capable. 10 ? 7 0x0 ro reserved 6 0 ro preamble suppressed not supported. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 142 revision 1.0 phy 1 and mii basic status register (0x04e C 0x04f): p1mbsr (continued) bit default r/w description bit is same a s: 5 0 ro auto- negotiation complete 1 = auto? negotiation complete. 0 = auto? negotiation not completed. b it [6 ] in p1sr 4 0 ro far ? end ? fault 1 = f ar ? end ? fault detected. 0 = n o far ? end ? fault detected. for 100 base ? fx fiber mode operation. b it [8 ] in p1sr 3 1 ro auto- negotiation capable 1 = auto? negotiation capable. 0 = n ot auto ? negotiation capable. 2 0 ro link status 1 = l ink is up. 0 = l ink is down. b it [5 ] in p1sr 1 0 ro jabber test not supported. 0 0 ro extended capable 1 = e xtended register capable. 0 = n ot extended register capable. phy 1 phyid low register (0x050 C 0x051): phy1ilr this register contains the phy id (low) for the switch port 1 function. bit default r/w description 15 ? 0 0x1430 ro phy 1 id low word low order phy 1 id bits. phy 1 phyid high register (0x052 C 0x053): phy1ihr this register contains the phy id (high) for the switch port 1 function. bit default r/w description 15 ? 0 0x0022 ro phy 1 id high word high order phy 1 id bits. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 143 revision 1.0 phy 1 auto?negotiation advertisement register (0x054 C 0x055): p1anar this register contains the auto ? negotiation advertisement bits for the switch port 1 function. bit default r/w description bit is same a s: 15 0 ro next page not supported. 14 0 ro reserved 13 0 ro remote fault not supported. 12 ? 11 00 ro reserved 10 1 rw pause (flow control capability) 1 = a dvertise pause ability. 0 = d o not advertise pause capability. b it [4 ] in p1cr4 9 0 rw reserved 8 1 rw adv ertise 100 bt full ? duplex 1 = a dvertise 100 bt full ? duplex capable. 0 = d o not advertise 100 bt full ? duplex capability. b it [3 ] in p1cr4 7 1 rw adv ertise 100 bt half ? duplex 1= a dvertise 100 bt half ? duplex capable. 0 = d o not advertise 100 bt half ? duplex capability. b it [2 ] in p1cr4 6 1 rw adv ertise 10 bt full ? duplex 1 = a dvertise 10 bt full ? duplex capable. 0 = d o not advertise 10 bt full ? duplex capability. b it [1 ] in p1cr4 5 1 rw adv ertise 10 bt half?duplex 1 = a dvertise 10 bt half ? duplex capable. 0 = d o not advertise 10 bt half ? duplex capability. b it [0 ] in p1cr 4 ? 0 0x01 ro selector field 802.3 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 144 revision 1.0 phy 1 auto?negotiation link partner ability register (0x056 C 0x057): p1anlpr this register contains the auto ? negotiation link partner ability bits for the switch port 1 function. bit default r/w description bit is same a s: 15 0 ro next page not supported. 14 0 ro lp ack not supported. 13 0 ro remote fault not supported. 12?11 00 ro reserved 10 0 ro pause link partner pause capability. bit [4] in p1sr 9 0 ro reserved 8 0 ro adv ertise 100bt full ? duplex link partner 100bt full - duplex capability. bit [3] in p1sr 7 0 ro adv ertise 100bt half ? duplex link partner 100 half ? duplex capability. bit [2] in p1sr 6 0 ro adv ertise 10bt full ? duplex link partner 10bt full ? duplex capability. bit [1] in p1sr 5 0 ro adv ertise 10bt half ? duplex link partner 10bt half ? duplex capability. bit [0] in p1sr 4?0 0x01 ro reserved phy 2 and mii basic control register (0x058 C 0x059): p2mbcr this register contains media independent interface (mii) control bits for the switch port 2 function as defined in the ieee 802.3 specification. bit default r/w description bit is same a s: 15 0 ro reserved 14 0 rw far?end loopback 1 = perform loop back, as follows: start: rxp1/rxm1 ( port 1) loop back: pmd/pma of port 2s phy end: txp1/txm1 ( port 1) 0 = normal operation. bit [8] in p2cr4 13 1 rw force 100bt 1 = f orce 100 mbps if auto - negotiation is disabled (bit [ 12 ]) 0 = f orce 10 mbps if auto - negotiation is disabled (bit [ 12 ]) bit [6] in p2cr4 12 1 rw auto - negotiation enable 1 = auto? negotiation enabled. 0 = auto? negotiation disabled. bit [7] in p2cr4 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 145 revision 1.0 phy 2 and mii basic control register (0x058 C 0x059): p2mbcr (continued) bit default r/w description bit is same a s: 11 0 rw power down 1 = power down. 0 = normal operation. bit [11] in p2cr4 10 0 ro isolate not supported. 9 0 rw /sc restart auto - negotiation 1 = restart auto ? negotiation . 0 = normal operation, bit [13] in p2cr4 8 1 rw force full duplex 1 = f orce full duplex. 0 = f orce half duplex. applies only when auto - negotiation is disabled (bit [ 12 ]). it is always in half duplex if auto - negotiation is enabled but failed. bit [5] in p2cr4 7 0 ro collision test not supported. 6 0 ro reserved 5 1 r/w hp_mdi -x 1 = hp auto mdi?x mode. 0 = micrel auto mdi?x mode. bit [15] in p2sr 4 0 rw force mdi?x 1 = force mdi?x. 0 = normal operation. bit [9] in p2cr4 3 0 rw disable auto mdi?x 1 = disable auto mdi?x. 0 = normal operation. bit [10] in p2cr4 2 0 rw disable far ? end ? fault 1 = d isable far ? end ? fault detection. 0 = n ormal operation. for 100 base ? fx fiber mode operation. bit [12] in p2cr4 1 0 rw disable transmit 1 = disable transmit. 0 = normal operation. bit [14] in p2cr4 0 0 rw reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 146 revision 1.0 phy 2 and mii basic status register (0x05a C 0x05b): p2mbsr this register contains the media independent interface (mii) status bits for the switch port 2 function bit default r/w description bit is same a s: 15 0 ro t4 capable 1 = 100base ? t4 capable. 0 = n ot 100base ? t4 capable. 14 1 ro 100 bt full capable 1 = 100base ? tx full ? duplex capable. 0 = n ot 100base ? tx full ? duplex capable. 13 1 ro 100 bt half capable 1 = 100base ? tx half ? duplex capable. 0 = n ot 100base ? tx half ? duplex capable. 12 1 ro 10 bt full capable 1 = 10base ? t full ? duplex capable. 0 = n ot 10base ? t full ? duplex capable. 11 1 ro 10 bt half capable 1 = 10base ? t half ? duplex capable. 0 = n ot 10base ? t half ? duplex capable. 10 ? 7 0x0 ro reserved 6 0 ro preamble suppressed not supported. 5 0 ro auto- negotiation complete 1 = auto? negotiation complete. 0 = auto? negotiation not completed. b it [6 ] in p2sr 4 0 ro far ? end ? fault 1 = f ar ? end ? fault detected. 0 = n o far ? end ? fault detected. for 100 base ? fx fiber mode operation. b it [8 ] in p2sr 3 1 ro auto- negotiation capable 1 = auto? negotiation capable. 0 = n ot auto ? negotiation capable. 2 0 ro link status 1 = l ink is up. 0 = l ink is down. b it [5 ] in p2sr 1 0 ro jabber test not supported. 0 0 ro extended capable 1 = e xtended register capable. 0 = n ot extended register capable. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 147 revision 1.0 phy 2 phyid low register (0x05c C 0x05d): phy2ilr this register contains the phy id (low) for the switch port 2 function. bit default r/w description 15 ? 0 0x1430 ro phy 2 id low word low order phy 2 id bits. phy 2 phyid high register (0x05e C 0x05f): phy2ihr this register contains the phy id (high) for the switch port 2 function. bit default r/w description 15 ? 0 0x0022 ro phy 2 id high word high order phy 2 id bits. phy 2 auto?negotiation advertisement register (0x060 C 0x061): p2anar this register contains the auto ? negotiation advertisement bits for the switch port 2 function. bit default r/w description bit is same a s: 15 0 ro next page not supported. 14 0 ro reserved 13 0 ro remote fault not supported. 12 ? 11 00 ro reserved 10 1 rw pause (flow control capability) 1 = a dvertise pause ability. 0 = d o not advertise pause capability. b it [4 ] in p2cr4 9 0 rw reserved 8 1 rw adv ertise 100 bt full ? duplex 1 = a dvertise 100 bt full ? duplex capable. 0 = d o not advertise 100 bt full ? duplex capability. b it [3 ] in p2cr4 7 1 rw adv ertise 100 bt half ? duplex 1= a dvertise 100 bt half ? duplex capable. 0 = d o not advertise 100 bt half ? duplex capability. b it [2 ] in p2cr4 6 1 rw adv ertise 10 bt full ? duplex 1 = a dvertise 10 bt full ? duplex capable. 0 = d o not advertise 10 bt full ? duplex capability. b it [1 ] in p2cr4 5 1 rw adv ertise 10 bt half?duplex 1 = a dvertise 10 bt half ? duplex capable. 0 = d o not advertise 10 bt half ? duplex capability. b it [0 ] in p2cr4 4 ? 0 0x01 ro selector field 802.3 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 148 revision 1.0 phy 2 auto?negotiation link partner ability register (0x062 C 0x063): p2anlpr this register contains the auto ? negotiation link partner ability bits for the switch port 2 function. bit default r/w description bit is same a s: 15 0 ro next page not supported. 14 0 ro lp ack not supported. 13 0 ro remote fault not supported. 12?11 00 ro reserved 10 0 ro pause link partner pause capability. bit [4] in p2sr 9 0 ro reserved 8 0 ro adv ertise 100bt full ? duplex link partner 100bt full ? duplex capability. bit [3] in p2sr 7 0 ro adv ertise 100bt half ? duplex link partner 100 half ? duplex capability. bit [2] in p2sr 6 0 ro adv ertise 10bt full ? duplex link partner 10bt full ? duplex capability. bit [1] in p2sr 5 0 ro adv ertise 10bt half ? duplex link partner 10bt half ? duplex capability. bit [0] in p2sr 4?0 0x01 ro reserved 0x0x064 C 0x065: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 149 revision 1.0 phy1 special control and status register (0x066 C 0x067): p1phyctrl this register contains control and status information of phy 1. bit default r/w description bit is same a s: 15 ? 6 0x000 ro reserved 5 0 ro polarity reverse 1 = p olarity is reversed. 0 = p olarity is not reversed. b it [ 13 ] in p1sr 4 0 ro mdi?x status 0 = mdi 1 = mdi ? x b it [7 ] in p1sr 3 0 rw force link 1 = f orce link pass. 0 = n ormal operation. b it [ 11 ] in p1scslmd 2 1 rw enable energy efficient ethernet (eee) on 10bte 1 = disable 10bte . 0 = enable 10bte . 1 0 rw remote (near?end) loopback 1 = p erform remote loopback at port 1's phy (rxp1/rxm1 ?> txp1/txm1) 0 = n ormal operation b it [9 ] in p1scslmd 0 0 rw reserved 0x068 C 0x069: reserved phy 2 special control and status register (0x06a C 0x06b): p2phyctrl this register contains control and status information of phy 2. bit default r/w description bit is same a s: 15 ? 6 0x000 ro reserved 5 0 ro polarity reverse 1 = p olarity is reversed. 0 = p olarity is not reversed. b it [ 13 ] in p2sr 4 0 ro mdi?x status 0 = mdi 1 = mdi ? x b it [7 ] in p2sr 3 0 rw force link 1 = f orce link pass. 0 = n ormal operation. b it [ 11 ] in p2scslmd 2 1 rw enable energy efficient ethernet (eee) on 10bte 1 = disable 10bte . 0 = enable 10bte . 1 0 rw remote (near?end) loopback 1 = perform remote loopback at port 2 's phy (rxp2/rxm2 ?> txp2/txm2 ) 0 = n ormal operation b it [9 ] in p2scslmd 0 0 rw reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 150 revision 1.0 port 1 control registers port 1 control register 1 (0x06c C 0x06d): p1cr1 this register contains control bits for the switch port 1 function. bit default r/w description 15 0 ro reserved 14 - 12 000 r/w port 1 led direct control these bits directly control the port 1 led pins. 0xx = normal led function as set up via reg. 0x00e C 0x00f, bits [9:8]. 100 = both port 1 leds off. 101 = port 1 led1 off, led0 on. 110 = port 1 led1 on, led0 off. 111 = both port 1 leds on. 11 0 rw source address filtering enable for mac address 2 1 = enable the source address filtering function when the sa matches mac address 2 in safmaca2 (0x0b6 C 0x0bb) . 0 = d is able source address filtering function. 10 0 rw source address filtering enable for mac address 1 1 = enable the source address filtering function when the sa matches mac address 1 in safmaca1 (0x0b0 C 0x0b5) . 0 = d is able source address filtering function. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 151 revision 1.0 port 1 control register 1 (0x06c C 0x06d): p1cr1 (continued) bit default r/w description 9 0 rw drop tagged packet enable 1 = e n able to drop tagged ingress packets. 0 = d isable to drop tagged ingress packets . 8 0 rw tx two queues select enable 1 = t he port 1 output queue is split into two priority queues (q0 and q1). 0 = s ingle output queue on port 1 . there is no priority differentiation even though packets are classified into high or low priority. 7 0 rw broadcast storm protection enable 1 = e nable broadcast storm protection for ingress packets on port 1. 0 = d isable broadcast storm protection. 6 0 rw diffserv priority classification enable 1 = e nable diffserv priority classification for ingress packets on port 1. 0 = d isable diffserv function. 5 0 rw 802.1p priority classification enable 1 = e nable 802.1p priority classification for ingress packets on port 1. 0 = d isable 802.1p. 4 ? 3 00 rw port ? based priority classification 00 = i ngress packets on port 1 are classified as priority 0 queue if diffserv or 802.1p classification is not enabled or fails to classify. 01 = i ngress packets on port 1 are classified as priority 1 queue if diffserv or 802.1p classification is not enabled or fails to classify. 10 = i ngress packets on port 1 are classified as priority 2 queue if diffserv or 802.1p classification is not enabled or fails to classify. 11 = i ngress packets on port 1 are classified as priority 3 queue if diffserv or 802.1p classification is not enabled or fails to classify. note : diffserv, 802.1p and port priority can be enabled at the same time. the ored result of 802.1p and dscp overwrites the port priority. 2 0 rw tag insertion 1 = w hen packets are output on port 1 , the switch adds 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. 0 = d isable tag insertion. 1 0 rw tag removal 1 = w hen packets are output on port 1 , the switch removes 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets r eceived without tags. 0 = d isable tag removal. 0 0 rw tx multiple queues select enable 1 = t he port 1 output queue is split into four priority queues (q0, q1, q2 and q3). 0 = s ingle output queue on port 1 . there is no priority differentiation even though packets are classified into high or low priority. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 152 revision 1.0 port 1 control register 2 (0x06e C 0x06f): p1cr2 this register contains control bits for the switch port 1 function. bit default r/w description 15 0 rw reserved 14 0 rw ingress vlan filtering 1 = t he switch discards packets whose vid port membership in vlan table bits [18:16] does not include the ingress port vid. 0 = n o ingress vlan filtering. 13 0 rw discard non pvid packets 1 = t he switch discards packets whose vid does not match the ingress port default vid. 0 = n o packets are discarded. 12 0 rw force flow control 1 = a lways enable flow control on the port, regardless of auto - negotiation result. 0 = t he flow control is enabled based on auto - negotiation result. 11 0 rw back pressure enable 1 = e nable ports half ? duplex back pressure. 0 = d isable ports half ? duplex back pressure. 10 1 rw transmit enable 1 = e nable packet transmission on the port. 0 = d isable packet transmission on the port. 9 1 rw receive enable 1 = e nable packet reception on the port. 0 = d isable packet reception on the port. 8 0 rw learning disable 1 = d isable switch address learning capability. 0 = e nable switch address learning. 7 0 rw sniffer port 1 = p ort is designated as a sniffer port and transmits packets that are monitored. 0 = p ort is a normal port. 6 0 rw receive sniff 1 = a ll packets received on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = n o receive monitoring. 5 0 rw transmit sniff 1 = a ll packets transmitted on the port are marked as monitored packets and forwar ded to the designated sniffer port. 0 = n o transmit monitoring. 4 0 rw reserved 3 0 rw user priority ceiling 1 = i f the packets priority field is greater than the user priority field in the port v id control register bit[15:13], replace the packets priority field with the user prior ity field in the port vid control register bit[15:13]. 0 = d o no t compare and replace the packets priority field. 2 ? 0 111 rw port vlan membership define the ports port vlan membership. bit [2] stands for the host port, bit [1] for port 2 , and bit [0] for port 1 . the port can only communicate within the membership. a 1 includes a port in the membershi p; a 0 excludes a port from the membership. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 153 revision 1.0 port 1 vid control register (0x070 C 0x071): p1vidcr this register contains the control bits for the switch port 1 function. this register has two main uses. it is associated with the ingress of untagged packets and used for egress tagging as well as being used f or address lookup and providing a default vid for the ingress of untagged or null?vid?tagged packets. bit default r/w description 15?13 000 rw default tag[15:13] ports default tag, containing user priority field bits. 12 0 rw default tag[12] ports default tag, containing the cfi bit. 11?0 0x001 rw default tag[11:0] ports default tag, containing the vid[11:0]. port 1 control register 3 (0x072 C 0x073): p1cr3 this register contains the control bits for the switch port 1 function. bit default r/w description 15?5 0x000 ro reserved 4 0 rw reserved 3?2 00 rw ingress limit mode these bits determine what kinds of frames are limited and counted against ingress rate limiting as follows: 00 = limit and count all frames. 01 = limit and count broadcast, multicast, and flooded unicast frames. 10 = limit and count broadcast and multicast frames only. 11 = limit and count broadcast frames only. 1 0 rw count inter frame gap count ifg bytes. 1 = each frames minimum inter frame gap. ifg bytes (12 per frame) are included in ingress and egress rate calculations. 0 = ifg bytes are not counted. 0 0 rw count preamble count preamble bytes. 1 = each frames preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. 0 = preamble bytes are not counted. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 154 revision 1.0 port 1 ingress rate control register 0 (0x074 C 0x075): p1ircr0 this register contains the port 1 ingress rate limiting control for priority 1 and priority 0. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw ingress data rate limit for pri ority 1 frames ingress p riority 1 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10 mbps or 100 mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw ingress data rate limit for pri ority 0 frames ingress p ri ority 0 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10 mbps or 100 mbps with no limit. table 23 . ingress or egress data rate limits data rate limit for ingress or egress 1 00bt for priority [3:0] register bit [14:8] or b it [6:0] 10bt for priority [3:0] register bit [14:8] or b it [6:0] 0x01 to 0x64 for the r ate matches 1mbps to 100mbps respectively 0x01 to 0x0a for the rate matches 1mbps to 10mbps respectively 0x00 (default) for the rate is no limit (full 100mbps) 0 x00 (default) for the rate is no limit (full 10mbps) 64 kbps 0x65 128 kbps 0x66 192 kbps 0x67 256 kbps 0x68 320 kbps 0x69 384 kbps 0x6a 448 kbps 0x6b 512 kbps 0x6c 576 kbps 0x6d 640 kbps 0x6e 704 kbps 0x6f 768 kbps 0x70 832 kbps 0x71 896 kbps 0x72 960 kbps 0x73 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 155 revision 1.0 port 1 ingress rate control register 1 (0x076 C 0x077): p1ircr1 this register contains the port 1 ingress rate limiting control bits for priority 3 and priority 2. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw ingress data rate limit for priority 3 frames ingress priority 3 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10 mbps or 100 mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw ingress data rate limit for priority 2 frames ingress p ri ority 2 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full r ate at 10mbps or 100 mbps with no limit. port 1 egress rate control register 0 (0x078 C 0x079): p1ercr0 this register contains the port 1 egress rate limiting control bits for priority 1 and priority 0. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw egress data rate limit for priority 1 frames egress priority 1 frames will be limited or discarded as shown in table 23 n ote: the default value 0x00 is full rate at 10mbps or 100 mbps with no limit. 7 0 rw egress rate limit control enable 1 = enable egress rate limit control. 0 = disable egress rate limit control. 6? 0 0x0 0 rw egress data rate limit for priority 0 frames egress p ri ority 0 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. port 1 egress rate control register 1 (0x07a C 0x07b): p1ercr1 this register contains the port 1 egress rate limiting control bits for priority 3 and priority 2. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw egress data rate limit for priority 3 frames egress p riority 3 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100 mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw egress data rate limit for priority 2 frames egress p ri ority 2 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 156 revision 1.0 port 1 phy special control/status, linkmd (0x07c C 0x07d): p1scslmd this register contains the linkmd control and status information of phy 1. bit default r/w description bit is same a s: 15 0 ro cdt_10m_short 1 = less than 10 meter short. 14 ? 13 00 ro cdt_result [00] = n ormal condition. [01] = o pen condition has been detected in cable. [10] = s hort condition has been detected in cable. [11] = c able diagnostic test has failed. 12 0 rw / sc cdt_enable 1 = c able diagnostic test is enabled. it is self ? cleared after the cd t test is done. 0 = i ndicates that the cable diagnostic test is completed and the status information is valid for reading . 11 0 rw force_link force link. 1 = f orce link pass. 0 = n ormal operation. b it [3 ] in p1phyctrl 10 1 rw reserved 9 0 rw remote (near?end) loopback 1 = p erform remote loopback at port 1's phy (rxp1/ rxm1 ?> txp1/txm1 ) 0 = n ormal operation b it [1 ] in p1phyctrl 8 ? 0 0x000 ro cdt_fault_count distance to the fault. its approximately 0.4m* cdt _f ault_ c ount. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 157 revision 1.0 port 1 control register 4 (0x07e C 0x07f): p1cr4 this register contains control bits for the switch port 1 function. bit default r/w description bit is same as : 15 0 rw reserved 14 0 rw disable transmit 1 = d isable the ports transmitter. 0 = n ormal operation. b it [1 ] in p1mbcr 13 0 rw /sc restart auto?negotiation 1 = r estart auto ? negotiation . 0 = n ormal operation. b it [9 ] in p1mbcr 12 0 rw disable far?end?fault 1 = d isable far ? end ? fault detection. 0 = n ormal operation. for 100 base ? fx fiber mode operation. b it [2 ] in p1mbcr 11 0 rw power down 1 = p ower down. 0 = n ormal operation. no change to registers setting. b it [ 11 ] in p1mbcr 10 0 rw disable auto mdi/mdi?x 1 = d isable a uto - mdi/mdi ? x function. 0 = e nable a uto - mdi/mdi ? x function. b it [3 ] in p1mbcr 9 0 rw force mdi?x 1 = i f a uto - mdi/mdi ? x is disabled, force phy into mdi ? x mode. 0 = d o not force phy into mdi ? x mode. b it [4 ] in p1mbcr 8 0 rw far?end loopback 1 = p erform loopback, as indicated: start: rxp2/rxm2 ( port 2). loopback: pmd/pma of port 1 s phy. end: txp2/txm2 ( port 2). 0 = n ormal operation. b it [ 14 ] in p1mbcr 7 1 rw auto?negotiation enable 1 = auto? negotiation is enabled. 0 = d isable auto ? negotiation , speed, and duplex are decided by bits[ 6 :5] of the same register. b it [ 12 ] in p1mbcr 6 1 rw force speed 1 = f orce 100bt if auto ? negotiation is disabled (bit [7]). 0 = f orce 10bt if auto ? negotiation is disabled (bit [7]). b it [ 13 ] in p1mbcr downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 158 revision 1.0 port 1 control register 4 (0x07e C 0x07f): p1cr4 (continued) bit default r/w description bit is same as: 5 1 rw force duplex 1 = f orce fu ll ? duplex if auto ? negotiation is disabled. 0 = force half ? duplex if auto ? negotiation is disabled . it is always in half duplex if auto ? negotiation is enabled but failed. b it [ 8 ] in p1mbcr 4 1 rw advertised flow control c apability 1 = a dvertise flow control (pause) capability. 0 = s uppress flow control (pause) capability from transmission to link partner. b it [ 10 ] in p1anar 3 1 rw advertised 100bt full?duplex c apability 1 = a dvertise 100bt full ? duplex capability. 0 = s uppress 100bt full ? duplex capability from transmission to link partner. b it [8 ] in p1anar 2 1 rw advertised 100bt half?duplex c apability 1 = a dvertise 100bt half ? duplex capability. 0 = s uppress 100bt half ? duplex capability from transmission to link partner. b it [7 ] in p1anar 1 1 rw advertised 10bt full?duplex c apability 1 = a dvertise 10bt full ? duplex capability. 0 = s uppress 10bt full ? duplex capability from transmission to link partner. b it [6 ] in p1anar 0 1 rw advertised 10bt half?duplex c apability 1 = a dvertise 10bt half ? duplex capability. 0 = s uppress 10bt half ? duplex capability from transmission to link partner. b it [5 ] in p1anar port 1 status register (0x080 C 0x081): p1sr this register contains the status bits for the switch port 1 function. bit default r/w description bit is same as : 15 1 rw hp_mdi -x 1 = hp auto - mdi ? x mode. 0 = micrel auto - mdi ? x mode. b it [5 ] in p1mbcr 14 0 ro reserved 13 0 ro polarity reverse 1 = p olarity is reversed. 0 = p olarity is not reversed. b it [5 ] in p1phyctrl 12 0 ro transmit flow control enable 1 = t ransmit flow control feature is active. 0 = t ransmit flow control feature is inactive. 11 0 ro receive flow control enable 1 = r eceive flow control feature is active. 0 = r eceive flow control feature is inactive. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 159 revision 1.0 port 1 status register (0x080 C 0x081): p1sr (continued) bit default r/w description bit is same as: 10 0 ro operation speed 1 = l ink speed is 100 mbps. 0 = l ink speed is 10 mbps. 9 0 ro operation duplex 1 = l ink duplex is full. 0 = l ink duplex is half. 8 0 ro far?end fault 1 = f ar ? end ? fault detected. 0 = n o far ? end ? fault detected. for 100 base ? fx fiber mode operation. b it [4 ] in p1mbsr 7 0 ro mdi? x s tatus 0 = mdi. 1 = mdi ? x. b it [4 ] in p1phyctrl 6 0 ro auto - negotiation done 1 = a uto - negotiation done. 0 = a uto - negotiation not done. b it [5 ] in p1mbsr 5 0 ro link status 1 = l ink good. 0 = l ink not good. b it [2] in p1mbsr 4 0 ro partner flow control capability 1 = l ink partner flow control (pause) capable. 0 = l ink partner not flow control (pause) capable. bi t [ 10 ] in p1anlpr 3 0 ro partner 100bt full?duplex capability 1 = l ink partner 100bt full ? duplex capable. 0 = l ink partner not 100bt full ? duplex capable. b it [8 ] in p1anlpr 2 0 ro partner 100bt half?duplex capability 1 = l ink partner 100bt half ? duplex capable. 0 = l ink partner not 100bt half ? duplex capable. b it [7 ] in p1anlpr 1 0 ro partner 10bt full?duplex capability 1 = l ink partner 10bt full ? duplex capable. 0 = l ink partner not 10bt full ? duplex capable. b it [6 ] in p1anlpr 0 0 ro partner 10bt half?duplex capability 1 = l ink partner 10bt half ? duplex capable. 0 = l ink partner not 10bt half ? duplex capable. b it [5 ] in p1anlpr 0x082 C 0x083: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 160 revision 1.0 port 2 control registers port 2 control register 1 (0x084 C 0x085): p2cr1 this register contains control bits for the switch port 2 function. bit default r/w description 15 0 ro reserved 14 - 12 000 r/w port 2 led direct control these bits directly control the port 2 led pins. 0xx = normal led function as set up via reg. 0x00e C 0x00f, bits [9:8]. 100 = both port 2 leds off. 101 = port 2 led1 off, led0 on. 110 = port 2 led1 on, led0 off. 111 = both port 2 leds on. 11 0 rw source address filtering enable mac address 2 1 = enable the source address filtering function when the sa matches the mac address 2 in safmaca2 (0x0b6 C 0x0bb). 0 = d is able source address filtering function. 10 0 rw source address filtering enable for mac address 1 1 = enable the source address filtering function when the sa matches the mac address 1 in safmaca1 (0x0b0 C 0x0b5) . 0 = d is able source address filtering function. 9 0 rw drop tagged packet enable 1 = e n able to drop tagged ingress packets. 0 = d isable to drop tagged ingress packets . 8 0 rw tx two queues select enable 1 = t he port 2 output queue is split into two priority queues (q0 and q1) 0 = s ingle output queue on port 2 . there is no priority differentiation even though packets are classified into high or low priority. 7 0 rw broadcast storm protection enable 1 = e nable broadcast storm protection for ingress packets on port 2. 0 = d isable broadcast storm protection. 6 0 rw diffserv priority classification enable 1 = e nable diffserv priority classification for ingress packets on port 2. 0 = d isable diffserv function. 5 0 rw 802.1p priority classification enable 1 = e nable 802.1p priority classification for ingress packets on port 2. 0 = d isable 802.1p. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 161 revision 1.0 port 2 control register 1 (0x084 C 0x085): p2cr1 (continued) bit default r/w description 4 ? 3 00 rw port?based priority classification 00 = i ngress packets on port 2 are classified as priority 0 queue if diffserv or 802.1p classification is not enabled or fails to classify. 01 = i ngress packets on port 2 are classified as priority 1 queue if diffserv or 802.1p classification is not enabled or fails to classify. 10 = i ngress packets on port 2 are classified as priority 2 queue if diffserv or 802.1p classification is not enabled or fails to classify. 11 = i ngress packets on port 2 are classified as priority 3 queue if diffserv or 802.1p classification is not enabled or fails to classify. note: diffserv, 802.1p and port priority can be enabled at the same time. the ored result of 802.1p and dscp overwrites the port priority. 2 0 rw tag insertion 1 = w hen packets are output on port 2 , the switch adds 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. 0 = d isable tag insertion. 1 0 rw tag removal 1 = w hen packets are output on port 2 , the switch removes 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. 0 = d isable tag removal. 0 0 rw tx multiple queues select enable 1 = t he port 2 output queue is s plit into four priority queues (q0, q1, q2 and q3). 0 = s ingle output queue on port 2 . there is no priority differentiation even though packets are classified into high or low priority. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 162 revision 1.0 port 2 control register 2 (0x086 C 0x087): p2cr2 this register contains the control bits for the switch port 2 function. bit default r/w description 15 0 rw reserved 14 0 rw ingress vlan filtering 1 = t he switch discards packets whose vid port membership in vlan table bits[ 18:16] does not include the ingress port vid. 0 = n o ingress vlan filtering. 13 0 rw discard non pvid packets 1 = t he switch discards packets whose vid does not match the ingress port default vid. 0 = n o packets are discarded. 12 0 rw force flow control 1 = a lways enable flow control on the port, regardless of a uto -n egotiation result. 0 = t he flow control is enabled based on a uto -n egotiation result. 11 0 rw back - pressure enable 1 = e nable ports half ? duplex back pressure. 0 = d isable ports half ? duplex back pressure. 10 1 rw transmit enable 1 = e nable packet transmission on the port. 0 = d isable packet transmission on the port. 9 1 rw receive enable 1 = e nable packet reception on the port. 0 = d isable packet reception on the port. 8 0 rw learning disable 1 = d isable switch address learning capability. 0 = e nable switch address learning. 7 0 rw sniffer port 1 = p ort is designated as a sniffer port and transmits packets that are monitored. 0 = p ort is a normal port. 6 0 rw receive sniff 1 = a ll packets received on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = n o receive monitoring. 5 0 rw transmit sniff 1 = a ll packets transmitted on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = n o transmit monitoring. 4 0 rw reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 163 revision 1.0 port 2 control register 2 (0x086 C 0x087): p2cr2 (continued) bit default r/w description 3 0 rw user priority ceiling 1 = i f the packets priority field is greater than the user priority field in the port v id control register bit[15:13], replace the packets priority field with the user prior ity field in the port vid control register bit[15:13]. 0 = d o no t compare and replace the packets priority field. 2 ? 0 111 rw port vlan membership define the ports port vlan membership. bit [2] stands for the host port, bit [1] for port 2 , and bit [ ] for port 1 . the port can only communicate within the membership. a 1 includes a port in the membershi p; a 0 excludes a port from the membership. port 2 vid control register (0x088 C 0x089): p2vidcr this register contains control bits for the switch port 2 fun ction. this p2vidcr control register serves two purposes: 1. associated with the ingress untagged packets, and used for egress tagging. 2. default vid for the ingress untagged or null?vid?tagged packets, and used for a ddress lookup bit default r/w description 15?13 000 rw default tag[15:13] ports default tag, containing user priority field bits. 12 0 rw default tag[12] ports default tag, containing cfi bit. 11?0 0x001 rw default tag[11:0] ports default tag, containing vid[11:0]. port 2 control register 3 (0x08a C 0x08b): p2cr3 this register contains control bits for the switch port 2 function. bit default r/w description 15?5 0x000 ro reserved 4 0 rw reserved 3?2 00 rw ingress limit mode these bits determine what kinds of frames are limited and counted against ingress rate limiting as follows: 00 = limit and count all frames. 01 = limit and count broadcast, multicast, and flooded unicast frames. 10 = limit and count broadcast and multicast frames only. 11 = limit and count broadcast frames only. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 164 revision 1.0 port 2 control register 3 (0x08a C 0x08b): p2cr3 (continued) bit default r/w description 1 0 rw count inter frame gap count ifg bytes. 1 = each frames minimum inter frame gap. ifg bytes (12 per frame) are included in ingress and egress rate limiting calculations. 0 = ifg bytes are not counted. 0 0 rw count preamble count preamble bytes. 1 = each frames preamble bytes (8 per frame) are included in ingress and egress rat e limiting calculations. 0 = preamble bytes are not counted. port 2 ingress rate control register 0 (0x08c C 0x08d): p2ircr0 this register contains the port 2 ingress rate limiting control bits for priority 1 and priority 0. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw ingress data rate limit for priority 1 frames ingress p riority 1 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or100 mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw ingress data rate limit for priority 0 frames ingress p ri ority 0 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. port 2 ingress rate control register 1 (0x08e C 0x08f): p2ircr1 this register contains the port 2 ingress rate limiting control bits for priority 3 and priority 2 frames. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw ingress data rate limit for priority 3 frames ingress priority 3 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10 mbps or 100 mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw ingress data rate limit for priority 2 frames ingress p ri ority 2 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10 mbps or 100 mbps with no limit. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 165 revision 1.0 port 2 egress rate control register 0 (0x090 C 0x091): p2ercr0 this register contains the port 2 egress rate limiting control bits for priority 1 and priority 0 frames. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw egress data rate limit for priority 1 frames egress priority 1 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. 7 0 rw egress rate limit control enable 1 = enable egress rate limit control. 0 = disable egress rate limit control. 6? 0 0x0 0 rw egress data rate limit for priority 0 frames egress p ri ority 0 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. port 2 egress rate control register 1 (0x092 C 0x093): p2ercr1 this register contains the port 2 egress rate limiting control bits for priority 3 and priority 2 frames. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw egress data rate limit for priority 3 frames egress p riority 3 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw egress data rate limit for priority 2 frames egress p ri ority 2 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 166 revision 1.0 port 2 phy special control/status, linkmd (0x094 C 0x095): p2scslmd this register contains the linkmd control and status information of phy 2. bit default r/w description bit is same a s: 15 0 ro cdt_10m_short 1 = less than 10 meter short. 14 ? 13 00 ro cdt_result [00] = n ormal condition. [01] = o pen condition has been detected in cable. [10] = s hort condition has been detected in cable. [11] = c able diagnostic test has failed. 12 0 rw / sc cdt_enable 1 = c able diagnostic test is enabled. it is self ? cleared after the cd t test is done. 0 = i ndicates that the cable diagnostic test is completed and the status information is valid for reading . 11 0 rw force_link 1 = f orce link pass. 0 = n ormal operation. b it [3 ] in p2phyctrl 10 1 rw reserved 9 0 rw remote (near?end) loopback 1 = p erform remote loopback at port 2's phy (rxp2/ rxm2 ?> txp2/txm2) 0 = n ormal operation b it [1 ] in p2phyctrl 8 ? 0 0x000 ro cdt_fault_count distance to the fault. its approximately 0.4m* cdt _f ault_ c ount. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 167 revision 1.0 port 2 control register 4 (0x096 C 0x097): p2cr4 this register contains the control bits for the switch port 2 function. bit default r/w description bit is same a s: 15 0 rw reserved 14 0 rw disable transmit 1 = d isable the ports transmitter. 0 = n ormal operation. b it [1 ] in p2mbcr 13 0 rw /sc restart auto - negotiation 1 = r estart a uto -n egotiation . 0 = n ormal operation. b it [9 ] in p2mbcr 12 0 rw disable far?end?fault 1 = d isable far ? end ? fault detection. 0 = n ormal operation. for 100 base ? fx fiber mode operation. b it [2 ] in p2mbcr 11 0 rw power down 1 = p ower down. 0 = n ormal operation. no change to registers setting b it [ 11 ] in p2mbcr 10 0 rw disable auto - mdi/mdi?x 1 = d isable a uto ? mdi/mdi ? x function. 0 = e nable a ut o? mdi/mdi ? x function. b it [3 ] in p2mbcr 9 0 rw force mdi?x 1 = i f a ut o? mdi/mdi ? x is disabled, force phy into mdi ? x mode. 0 = d o not force phy into mdi ? x mode. b it [4 ] in p2mbcr 8 0 rw far?end loopback 1 = p erform loopback, as indicated: start: rxp1/rxm1 ( port 1). loopback: pmd/pma of port 2 s phy. end: txp1/txm1 ( port 1). 0 = n ormal operation. b it [ 14 ] in p2mbcr 7 1 rw auto?negotiation enable 1 = auto? negotiation is enabled. 0 = d isable a uto -n egotiation , speed, and duplex are decided by bits[ 6:5] of the same register. b it [ 12 ] in p2mbcr 6 1 rw force speed 1 = f orce 100bt if a uto -n egotiation is disabled (bit [7]). 0 = f orce 10bt if a uto -n egotiation is disabled (bit [7]). b it [ 13 ] in p2mbcr downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 168 revision 1.0 port 2 control register 4 (0x096 C 0x097): p2cr4 (continued) bit default r/w description bit is same a s: 5 1 rw force duplex 1 = f orce full duplex if a uto -n egotiation is disabled. 0 = force half duplex if a uto -n egotiation is disabled . it is always in half duplex if a uto -n egotiation is enabled but failed. b it [8 ] in p2mbcr 4 1 rw advertised flow control c apability 1 = a dvertise flow control (pause) capability. 0 = s uppress flow control (pause) capability from transmission to link partner. b it [ 10 ] in p2anar 3 1 rw advertised 100bt full?duplex c apability 1 = a dvertise 100bt full ? duplex capability. 0 = s uppress 100bt full ? duplex capability from transmission to link partner. b it [8 ] in p2anar 2 1 rw advertised 100bt half?duplex c apability 1 = a dvertise 100bt half ? duplex capability. 0 = s uppress 100bt half ? duplex capability from transmission to link partner. b it [7 ] in p2anar 1 1 rw advertised 10bt full?duplex c apability 1 = a dvertise 10bt full ? duplex capability. 0 = s uppress 10bt full ? duplex capability from transmission to link partner. b it [6 ] in p2anar 0 1 rw advertised 10bt half?duplex c apability 1 = a dvertise 10bt half ? duplex capability. 0 = s uppress 10bt half ? duplex capability from transmission to link partner. b it [5 ] in p2anar downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 169 revision 1.0 port 2 status register (0x098 C 0x099): p2sr this register contains the status bits for the switch port 2 function. bit default r/w description bit is same a s: 15 1 rw hp_mdix 1 = hp auto ? mdi ? x mode. 0 = micrel auto mdi ? x mode. b it [5 ] in p2mbcr 14 0 ro reserved 13 0 ro polarity reverse 1 = p olarity is reversed. 0 = p olarity is not reversed. b it [5 ] in p2 phyctrl 12 0 ro transmit flow control enable 1 = t ransmit flow control feature is active. 0 = t ransmit flow control feature is inactive. 11 0 ro receive flow control enable 1 = r eceive flow control feature is active. 0 = r eceive flow control feature is inactive. 10 0 ro operation speed 1 = l ink speed is 100mbps. 0 = l ink speed is 10mbps. 9 0 ro operation duplex 1 = l ink duplex is full. 0 = l ink duplex is half. 8 0 ro far?end fault 1 = f ar ? end ? fault detected. 0 = n o far ? end ? fault detected. for 100 base ? fx fiber mode operation. b it [4 ] in p2mbsr 7 0 ro mdi? x s tatus 0 = mdi. 1 = mdi ? x. b it [4 ] in p2 phyctrl 6 0 ro auto - negotiation done 1 = a uto - negotiation done. 0 = a uto - negotiation not done. b it [5 ] in p2mbsr 5 0 ro link status 1 = l ink good. 0 = l ink not good. b it [2 ] in p2mbsr 4 0 ro partner flow control capability 1 = l ink partner flow control (pause) capable. 0 = l ink partner not flow control (pause) capable. b it [ 10 ] in p2 anlpr 3 0 ro partner 100bt full?duplex capability 1 = l ink partner 100bt full ? duplex capable. 0 = l ink partner not 100bt full ? duplex capable. b it [8 ] in p2anlpr downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 170 revision 1.0 port 2 status register (0x098 C 0x099): p2sr (continued) bit default r/w description bit is same a s: 2 0 ro partner 100bt half?duplex capability 1 = l ink partner 100bt half ? duplex capable. 0 = l ink partner not 100bt half ? duplex capable. b it [7 ] in p2anlpr 1 0 ro partner 10bt full?duplex capability 1 = l ink partner 10bt full ? duplex capable. 0 = l ink partner not 10bt full ? duplex capable. b it [6 ] in p2anlpr 0 0 ro partner 10bt half?duplex capability 1 = l ink partner 10bt half ? duplex capable. 0 = l ink partner not 10bt half ? duplex capable. b it [5 ] in p2anlpr 0x09a C 0x09b: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 171 revision 1.0 port 3 control registers port 3 control register 1 (0x09c C 0x09d): p3cr1 this register contains control bits for the switch port 3 function. bit default r/w description 15?10 0x00 ro reserved 9 0 rw drop tagged packet enable 1 = e n able to drop tagged ingress packets. 0 = d isable to drop tagged ingress packets . 8 0 rw tx two queues select enable 1 = t he port 3 output queue is split into two priority queues (q0 and q1). 0 = s ingle output queue on port 3 . there is no priority differentiation even though packets are classified into high or low priority. 7 0 rw broadcast storm protection enable 1 = e nable broadcast storm protection for ingress packets on port 3. 0 = d isable broadcast storm protection. 6 0 rw diffserv priority classification enable 1 = e nable diffserv priority classification for ingress packets o n port 3. 0 = d isable diffserv function. 5 0 rw 802.1p priority classification enable 1 = e nable 802.1p priority classification for ingress packets on port 3. 0 = d isable 802.1p. 4 ? 3 00 rw port?based priority classification 00 = i ngress packets on port 3 are classified as priority 0 queue if diffserv or 802.1p classification is not enabled or fails to classify. 01 = i ngress packets on port 3 are classified as priority 1 queue if diffserv or 802.1p classification is not enabled or fails to classify. 10 = i ngress packets on port 3 are classified as priority 2 queue if diffserv or 802.1p classification is not enabled or fails to classify. 11 = i ngress packets on port 3 are classified as priority 3 queue if diffserv or 802.1p classification is not enabled or fails to classify. note: diffserv, 802.1p and port priority can be enabled at the same time. the ored res ult of 802.1p and dscp overwrites the port priority. 2 0 rw tag insertion 1 = w hen packets are output on port 3 , the switch adds 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. 0 = d isable tag insertion. 1 0 rw tag removal 1 = w h en packets are output on port 3 , the switch removes 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. 0 = d isable tag removal. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 172 revision 1.0 port 3 control register 1 (0x09c C 0x09d): p3cr1 (continued) bit default r/w description 0 0 rw tx multiple queues select enable 1 = t he port 3 output queue is split into four priority queues (q0, q1, q2 and q3). 0 = s ingle output queue on port 3 . there is no priority differentiation even though packets are classified into high or low priority. port 3 control register 2 (0x09e C 0x09f): p3cr2 this register contains control bits for the switch port 3 function. bit default r/w description 15 0 rw reserved 14 0 rw ingress vlan filtering 1 = t he switch discards packets whose vid port membership in vlan table bits[ 18:16] does not include the ingress port vid. 0 = n o ingress vlan filtering. 13 0 rw discard non pvid packets 1 = t he switch discards packets whose vid does not match the ingress port default vid. 0 = n o packets are discarded. 12 0 rw reserved 11 0 rw back pressure enable 1 = e nable ports half ? duplex back pressure. 0 = d isable ports half ? duplex back pressure. 10 1 rw transmit enable 1 = e nable packet transmission on the port. 0 = d isable packet transmission on the port. 9 1 rw receive enable 1 = e nable packet reception on the port. 0 = d isable packet reception on the port. 8 0 rw learning disable 1 = d isable switch address learning capability. 0 = e nable switch address learning. 7 0 rw sniffer port 1 = p ort is designated as a sniffer port and transmits packets that are monitored. 0 = p ort is a normal port. 6 0 rw receive sniff 1 = a ll packets received on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = n o receive monitoring. 5 0 rw transmit sniff 1 = a ll packets transmitted on the port are marked as monitored packets and forwarded to the designated sniffer port. 0 = n o transmit monitoring. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 173 revision 1.0 port 3 control register 2 (0x09e C 0x09f): p3cr2 (continued) bit default r/w description 4 0 rw reserved 3 0 rw user priority ceiling 1 = i f the packets priority field is greater than the user priority field in the port v id control register bit[15:13], replace the packets priority field with the user priority f ield in the port vid control register bit[15:13]. 0 = d o no t compare and replace the packets priority field. 2 ? 0 111 rw port vlan membership define the ports port vlan membership. bit [2] stands for the host port, bit [1] for port 2 , and bit [0] for port 1 . the port can only communicate within the membership. a 1 includes a port in the membershi p; a 0 excludes a port from the membership. port 3 vid control register (0x0a0 C 0x0a1): p3vidcr this register contains control bits for the switch port 3 function. this p3vidcr control register serves two purposes: 1. associated with the ingress untagged packets, and used for egress tagging. 2. default vid for the ingress untagged or null ? vid ? tagged packets, and used for address lookup bit default r/w description 15?13 000 rw default tag[15:13] ports default tag, containing user priority field bits. 12 0 rw default tag[12] ports default tag, containing cfi bit. 11?0 0x001 rw default tag[11:0] ports default tag, containing vid[11:0]. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 174 revision 1.0 port 3 control register 3 (0x0a2 C 0x0a3): p3cr3 this register contains control bits for the switch port 3 function. bit default r/w description 15?8 0x00 ro reserved 7 0 rw reserved 6?4 0 00 rw reserved 3?2 00 rw ingress limit mode these bits determine what kinds of frames are limited and counted against ingress rate limiting as follows: 00 = limit and count all frames. 01 = limit and count broadcast, multicast, and flooded unicast frames. 10 = limit and count broadcast and multicast frames only. 11 = limit and count broadcast frames only. 1 0 rw count inter frame gap count ifg bytes. 1 = each frames minimum inter frame gap. ifg bytes (12 per frame) are included in ingress and egress rate limiting calculations. 0 = ifg bytes are not counted. 0 0 rw count preamble count preamble bytes. 1 = each frames preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. 0 = preamble bytes are not counted. port 3 ingress rate control register 0 (0x0a4 C 0x0a5): p3ircr0 this register contains the port 3 ingress rate limiting control bits for priority 1 and priority 0. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw ingress data rate limit for priority 1 frames ingress p riority 1 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw ingress data rate limit for priority 0 frames ingress p ri ority 0 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 175 revision 1.0 port 3 ingress rate control register 1 (0x0a6 C 0x0a7): p3ircr1 this register contains the port 3 ingress rate limiting control bits for priority 3 and priority 2. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw ingress data rate limit for priority 3 frames ingress priority 3 frames will be limited or discarded as shown in table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. 7 0 rw reserved 6? 0 0x0 0 rw ingress data rate limit for priority 2 frames ingress p ri ority 2 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. port 3 egress rate control register 0 (0x0a8 C 0x0a9): p3ercr0 this register contains the port 3 egress rate limiting control bits for priority 1 and priority 0. bit default r/w description 15 0 rw reserved 14?8 0x0 0 rw egress data rate limit for priority 1 frames egress priority 1 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. 7 0 rw egress rate limit control enable 1 = enable egress rate limit control. 0 = disable egress rate limit control. 6? 0 0x0 0 rw egress data rate limit for priority 0 frames egress p ri ority 0 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. port 3 egress rate control register 1 (0x0aa C 0x0ab): p3ercr1 this register contains the port 3 egress rate limiting control bits for priority 3 and priority 2. bit default r/w description 15 0 rw reserved 14?8 0x00 rw egress data rate limit for priority 3 frames egress p riority 3 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 10mbps with no limit. 7 0 rw reserved 6?0 0x00 rw egress data rate limit for priority 2 frames egress p ri ority 2 frames will be limited or discarded as shown in the table 23 . n ote: the default value 0x00 is full rate at 10mbps or 100mbps with no limit. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 176 revision 1.0 switch global control registers switch global control register 8 (0x0ac C 0x0ad): sgcr8 this register contains the global control bits for the switch function. bit default r/w description 15?14 10 rw two queue priority mapping these bits determine the mapping between the priority of the incoming frames and the destinat ion on - chip queue in a two queue configuration which uses egress queues 0 and 1. 00 = egress queue 1 receives priority 3 frames egress queue 0 receives priority 0, 1, 2 frames 01 = egr ess queue 1 receives priority 1, 2, 3 frames egress queue 0 receives priority 0 frames 10 = egress queue 1 receives priority 2, 3 frames egress queue 0 receives priority 0, 1 frames 11 = egress queue 1 receives priority 1, 2, 3 frames egress queue 0 receives priority 0 frames 13?11 000 ro reserved 10 0 rw / sc flush dynamic mac table before flushing the dynamic mac table, switch address learning must be disabled by setti ng bit[8] in the p1cr2, p2cr2 and p3cr2 registers. 9 0 rw flush static mac table 1 = e nable f lush static mac table for spanning tree application 0 = disable f lush static mac table for spanning tree application 8 0 rw port 3 tail tag mode enable 1 = e nable tail tag mode 0 = disable tail tag mode 7?0 0x00 rw force pause off iteration limit time enable 0x01 C 0xff = e nable to force pause off iteration limit time (a unit number is 160ms) 0x00 = disable force pause off iteration limit downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 177 revision 1.0 switch global control register 9 (0x0ae C 0x0af): sgcr9 this register contains the global control bits for the switch function. bit default r/w description 15?11 0x00 ro reserved 10?8 000 rw forwarding invalid frame define the forwarding port for frame with invalid vid. bit [10] stands for the host port, b it [9] for port 2, and bit [8] for port 1. 7?6 00 rw reserved 5 0 rw enable insert source port pvid tag when untagged frame from port 3 to port 2 1 = enable 0 = disable 4 0 rw enable insert source port pvid tag when untagged frame from port 3 to port 1 1 = enable 0 = disable 3 0 rw enable insert source port pvid tag when untagged frame from port 2 to port 3 1 = enable 0 = disable 2 0 rw enable insert source port pvid tag when untagged frame from port 2 to port 1 1 = enable 0 = disable 1 0 rw enable insert source port pvid tag when untagged frame from port 1 to port 3 1 = enable 0 = disable 0 0 rw enable insert source port pvid tag when untagged frame from port 1 to port 2 1 = enable 0 = disable downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 178 revision 1.0 source address filtering registers source address filtering mac address 1 register low (0x0b0 C 0x0b1): safmaca1l r egister bit fields for the low word of mac address 1. bit default value r/w description 15?0 0x0000 rw source filtering mac address1 low the least significant word of mac address 1. source address filtering mac address 1 register middle (0x0b2 C 0x0b3): safmaca1m r egister bit fields for the middle word of mac address 1. bit default value r/w description 15?0 0x0000 rw source filtering mac address middle 1 the middle word of mac address 1. source address filtering mac address 1 register high (0x0b4 C 0x0b5): safmaca1h r egister bit fields for the high word of mac address 1. bit default value r/w description 15?0 0x0000 rw source filtering mac address high 1 the most significant word of mac address 1. source address filtering mac address 2 register low (0x0b6 C 0x0b7): safmaca2l register bit fields for the low word of mac address 2. bit default value r/w description 15?0 0x0000 rw source filtering mac address low 2 the least significant word of mac address 2. source address filtering mac address 2 register middle (0x 0b8 C 0x0b9): safmaca2m r egister bit fields for the middle word of mac address 2. bit default value r/w description 15?0 0x0000 rw source filtering mac address middle 2 the middle word of mac address 2. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 179 revision 1.0 source address filtering mac address 2 register high (0x0b a C 0x0bb): safmaca2h r egister bit fields for the high word of mac address 2. bit default value r/w description 15?0 0x0000 rw source filtering mac address high 2 the most significant word of mac address 2. 0x0bc C 0x0c7: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 180 revision 1.0 txq rate control registers port 1 txq rate control register 1 (0x0c8 C 0x0c9): p1txqrcr1 this register contains the q2 and q3 rate control bits for port 1. bit default value r/w description 15 1 rw port 1 transmit queue 2 (high) ratio control 0 = strict priority. port 1 will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1 = bit[ 14:8 ] reflect the number of packet s allow to tra nsmit from this priority queue 2 within a certain time. 14?8 0x04 rw port 1 transmit queue 2 (high) ratio this ratio indicates the number of packet for high - priority packet can transmit within a given period. 7 1 rw port 1 transmit queue 3 (highest) ratio control 0 = strict priority. port 1 will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1 = bit[ 6:0 ] reflect the number of packet s allow to transmit from this priority queue 3 within a certain time. 6?0 0x08 rw port 1 transmit queue 3 (highest) ratio this ratio indicates the number of packet for highest priority packet can transmit within a given period. port 1 txq rate control register 2 (0x0ca C 0x0cb): p1txqrcr2 this register contains the q0 and q1 rate control bits for port 1. bit default value r/w description 15 1 rw port 1 transmit queue 0 (lowest) ratio control 0 = strict priority. port 1 will transmit all the packets from this priorit y queue 0 after transmit higher priority queue. 1 = bit[ 14:8 ] reflect the number of packet s allow to transmit from this priority queue 0 within a certain time. 14?8 0x01 rw port 1 transmit queue 0 (lowest) ratio this ratio indicates the number of packet for lowest priority packet can transmit wit hin a given period. 7 1 rw port 1 transmit queue 1 (low) ratio control 0 = strict priority. port 1 will transmit all the packets from this priorit y queue 1 before transmit lower priority queue. 1 = bit[ 6:0 ] reflect the number of packet s allow to tra nsmit from thi s priority queue 1 within a certain time. 6?0 0x02 rw port 1 transmit queue 1 (low) ratio this ratio indicates the number of packet for low priority packet can transmit withi n a given period. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 181 revision 1.0 port 2 txq rate control register 1 (0x0cc C 0x0cd): p2txqrcr1 this register contains the q2 and q3 rate control bits for port 2. bit default value r/w description 15 1 rw port 2 transmit queue 2 (high) ratio control 0 = strict priority. p ort 2 will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1 = bit[ 14:8 ] reflect the number of packet s allow to transmit from this priority queue 2 within a certain time. 14?8 0x04 rw port 2 transmit queue 2 (high) ratio this ratio indicates the number of packet for high priority packet can transmit withi n a given period. 7 1 rw port 2 transmit queue 3 (highest) ratio control 0 = strict priority. p ort 2 will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1 = bit[ 6:0 ] ref lect the number of packet s allow to transmit from this priority queue 3 within a certain time. 6?0 0x08 rw port 2 transmit queue 3 (highest) ratio this ratio indicates the number of packet for highest priority packet can transmit within a given period. port 2 txq rate control register 2 (0x0ce C 0x0cf): p2txqrcr2 this register contains the q0 and q1 rate control bits for port 2. bit default value r/w description 15 1 rw port 2 transmit queue 0 (lowest) ratio control 0 = strict priority. p ort 2 will transmit all the packets from this priority queue 0 after transmit higher priority queue. 1 = bit[ 14:8 ] reflect the number of packet s allow to transmit from this priority queue 0 within a certain time. 14?8 0x01 rw port 2 transmit queue 0 (lowest) ratio this ratio indicates the number of packet for lowest priority packet can transmit wit hin a given period. 7 1 rw port 2 transmit queue 1 (low) ratio control 0 = strict priority. p ort 2 will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1 = bit[ 6:0 ] reflect the number of packet s allow to transmit from this priority queue 1 within a certain time. 6?0 0x02 rw port 2 transmit queue 1 (low) ratio this ratio indicates the number of packet for low priority packet can transmit within a given period. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 182 revision 1.0 port 3 txq rate control register 1 (0x0d0 C 0x0d1): p3txqrcr1 this register contains the q2 and q3 rate control bits for port 3. bit default value r/w description 15 1 rw port 3 transmit queue 2 (high) ratio control 0 = strict priority. port 3 will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1 = bit[ 14:8 ] reflect the number of packet s allow to transmit from this priority queue 2 within a certai n time. 14?8 0x04 rw port 3 transmit queue 2 (high) ratio this ratio indicates the number of packet for high priority packet can transmit withi n a given period. 7 1 rw port 3 transmit queue 3 (highest) ratio control 0 = strict priority. port 3 will transmit all the packets from this priority queue 3 before transmit lower priority queue. 1 = bit[ 6:0 ] reflect the number of packet s allow to transmit from this priority queue 3 within a certain time. 6?0 0x08 rw port 3 transmit queue 3 (hig hest) ratio this ratio indicates the number of packet for highest priority packet can transmit within a given period. port 3 txq rate control register 2 (0x0d2 C 0x0d3): p3txqrcr2 this register contains the q0 and q1 rate control bits for port 3. bit default value r/w description 15 1 rw port 3 transmit queue 0 (lowest) ratio control 0 = strict priority. port 3 will transmit all the packets from this priority queue 0 after transmit higher priority queue. 1 = bit[ 14:8 ] reflect the number of packet s allow to transmit from this priority queue 0 within a certain time. 14?8 0x01 rw port 3 transmit queue 0 (lowest) ratio this ratio indicates the number of packet for lowest priority packet can transmit wit hin a given period. 7 1 rw port 3 transmit queue 1 (low) ratio control 0 = strict priority. port 3 will transmit all the packets from this priority queue 1 before transmit lower priority queue. 1 = bit[ 6:0 ] reflect the number of packet s allow to transmit from this priority queue 1 within a certain time. 6?0 0x02 rw port 3 transmit queue 1 (low) ratio this ratio indicates the number of packet for low priority packet can transmit withi n a given period. 0x0d4 C 0x0d5: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 18 3 revision 1.0 input and output multiplex selection registers input and output multiplex selection register (0x0d6 C 0x0d7): iomxsel this register is used to select input/output pin functions of pins 53, 54, and 55. bit default r/w description 15?12 0x0 ro reserved 11 1 rw reserved 10 1 rw reserved 9 1 rw reserved 8 1 rw reserved 7 1 rw reserved 6 1 rw reserved 5 1 rw selection of eesk or gpio3 on pin 53 1 = this pin is used for eesk (default), serial eeprom clock. 0 = this pin is used for gpio3. 4 1 rw reserved 3 1 rw reserved 2 1 rw selection of eedio or gpio4 on pin 54 1 = this pin is used for eedio (default), serial eeprom data. 0 = this pin is used for gpio4. 1 1 rw selection of eecs or gpio5 on pin 55 1 = this pin is used for eecs (default), serial eeprom chip select. 0 = this pin is used for gpio5. 0 1 rw reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 184 revision 1.0 configuration status and serial bus mode registers configuration status and serial bus mode register (0x0d8 C 0x0d9): cfgr this register is used to select fiber mode if desired. bit default r/w description 15?8 0x00 ro reserved 7 1 rw selection of port 2 mode of operation 1 = select copper mode 0 = select fiber mode (bypass mlt3 encoder/decoder, scrambler and descrambler) . fiber mode is available only for the ksz8462 fhl. when fiber mode is selected, bit [13] in dsp_cntrl_6 (0x734 C 0x735) should be cleared. 6 1 rw selection of port 1 mode of operation 1 = select copper mode 0 = select fiber mode (bypass mlt3 encoder/decoder, scrambler and descrambler) . fiber mode is available only for the ksz8462 fhl. when fiber mode is selected, bit [13] in dsp_cntrl_6 (0x734 C 0x735) should be cleared. 5?4 11 ro reserved 3 ?0 0xe rw reserved 0x0da C 0x0db: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 185 revision 1.0 auto -negotiation next page registers port 1 auto?negotiation next page transmit register (0x0dc C 0x0dd): p1anpt t his register contains the port 1 auto ? negotiation next p age transmit related bits . bit default r/w description 15 0 ro next page next p age (np) is used by the n ext p age function to indicate whether or not this is the last n ext p age to be transmitted. np shall be set as follows: 1 = a dditional next page(s) will follow. 0 = l ast page. 14 0 ro reserved 13 1 ro message page message p age (mp) is used by the n ext p age function to differentiate a m essage p age from an u nformatted p age. mp shall be set as follows: 1 = message p age . 0 = unformatted p age . 12 0 ro acknowledge 2 ackno wledge 2 (ack2) is used by the next page function to indicate that a device has the ability to comply with the message. ack2 shall be set as follows: 1 = able to comply with message. 0 = unable to comply with message. 11 0 ro toggle toggle (t) is used by the a rbitration function to e nsure synchronization with the link partner during n ext p age exchange. this bit shall always take the opposite value of the t oggle bit in the previously exchanged l ink c ode word. the initial value of the t oggle bit in the first n ext p age transmitted is the inverse of bit [ 11 ] in the base l ink c ode word and, therefore, may assume a value of logic one o r zero. the toggle bit shall be set as follows: 1 = p revious value of the transmitted link code word equal to logic zero. 0 = p revious value of the transmitted link code word equal to logic one. 10?0 0x001 rw message and unformatted code field message/unformatted code field bits[ 10:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 186 revision 1.0 port 1 auto?negotiation link partner received next page register (0x0de C 0x0df): p1alprnp this register contains the port 1 auto ? negotiation link partner received next p age related bits . bit default r/w description 15 0 ro next page next page (np) is used by the n ext p age function to indicate whether or not this is the last n ext p age to be transmitted. np shall be set as follows: 1 = a dditional n ext p age(s) will follow. 0 = l ast page. 14 0 ro acknowledge acknowledge (ack) is used by the auto ? negotiation function to indicate that a device has successfully received its l ink p artners link code word. the acknowledge bit is encoded in bit [ 14 ] regardless of the value of the s elector f ield or l ink c ode word encoding. if no n ext p age information is to be sent, this bit shall be set to logic one in the l ink c ode word after the reception of at least three consecutive and consistent flp bursts (ignoring the a cknowledge bit value). 13 0 ro message page message page (mp) is used by the n ext p age function to differentiate a m essage p age from an u nformatted p age. mp shall be set as follows: 1 = message p age . 0 = unformatted p age . 12 0 ro acknowledge 2 ackno wledge 2 (ack2) is used by the next page function to indicate that a device has the ability to comply with the message. ack2 shall be set as follows: 1 = able to comply with message. 0 = unable to comply with message. 11 0 ro toggle toggle (t) is used by the arbitration function t o e nsure synchronization with the link partner during n ext p age exchange. this bit shall always take the opposite value of the t oggle bit in the previously exchanged l ink c ode word. the initial value of the t oggle bit in the first n ext p age transmitted is the inverse of bit [ 11 ] in the base l ink c ode word and, therefore, may assume a value of logic one o r zero. the toggle bit shall be set as follows: 1 = p revious value of the transmitted l ink c ode word equal to logic zero. 0 = p revious value of the transmitted l ink c ode word equal to logic one. 10?0 0x000 ro message and unformatted code field message/unformatted code field bits[ 10:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 187 revision 1.0 eee and link partner advertisement registers port 1 eee and link partner advertisement register (0x0e0 C 0x0e1): p1eeea this register contains the port 1 eee advertisement and link partner advertisement information. note that eee is not supported in fiber mode . bit default r/w description 15 0 ro reserved 14 0 ro 10gbase?kr eee 1 = link partner eee is supported for 10gbase?kr. 0 = link partner eee is not supported for 10gbase?kr. 13 0 ro 10gbase?kx4 eee 1 = link partner eee is supported for 10gbase?kx4. 0 = link partner eee is not supported for 10gbase?kx4. 12 0 ro 1000base?kx eee 1 = link partner eee is supported for 1000base?kx. 0 = link partner eee is not supported for 1000base?kx. 11 0 ro 10gbase?t eee 1 = link partner eee is supported for 10gbase?t. 0 = link partner eee is not supported for 10gbase?t. 10 0 ro 1000base?t eee 1 = link partner eee is supported for 1000base?t. 0 = link partner eee is not supported for 1000base?t. 9 0 ro 100base?tx eee 1 = link partner eee is supported for 100base?tx. 0 = link partner eee is not supported for 100base?tx. 8C7 00 ro reserved 6 0 ro 10gbase?kr eee 1 = port 1 eee is supported for 10gbase?kr. 0 = port 1 eee is not supported for 10gbase?kr. 5 0 ro 10gbase?kx4 eee 1 = port 1 eee is supported for 10gbase?kx4. 0 = port 1 eee is not supported for 10gbase?kx4. 4 0 ro 1000base?kx eee 1 = port 1 eee is supported for 1000base?kx. 0 = port 1 eee is not supported for 1000base?kx. 3 0 ro 10gbase?t eee 1 = port 1 eee is supported for 10gbase?t. 0 = port 1 eee is not supported for 10gbase?t. 2 0 ro 1000base?t eee 1 = port 1 eee is supported for 1000base?t. 0 = port 1 eee is not supported for 1000base?t. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 188 revision 1.0 port 1 eee and link partner advertisement register (0x0e0 C 0x0e1): p1eee ( continued) bit default r/w description 1 1 rw 100base?tx eee 1 = port 1 eee is supported for 100base?tx. 0 = port 1 eee is not supported for 100base?tx. to disable eee capability, clear the port 1 next page enable bit in the pcseeec register (0x0f3). 0 0 ro reserved port 1 eee wake error count register (0x0e2 C 0x0e3): p1eeewec this register contains the port 1 eee wake error count information. note that eee is not supported in fiber mode. bit default value r/w description 15?0 0x0000 rw port 1 eee wake error count this counter is incremented by each transition of lpi_wake_timer_done from false to true. it means the wake - up time is longer than 20.5 s. the value will be held at all ones in the case of overflow and will be cleared to zero after this register is read. port 1 eee control/status and auto?negotiation expansion register (0x0e4 C 0x0e5): p1eeecs this register contains the port 1 eee control/status and auto ? negotiation expansion information. note that eee is not supported in fiber mode . bit default r/w description 15 1 rw reserved 14 0 ro hardware 100bt eee enable status 1 = 100bt eee is enabled by hardware based np exchange . 0 = 100bt eee is disabled . 13 0 ro/lh (latching high) tx lpi received 1 = indicates that the transmit pcs has received low power idle (lpi) signaling one or more times since t he register was last read. 0 = indicates that the pcs has not received low power idle (lpi) signaling. the status will be latched high and stay that way until cleared. to clear this stat us bit, a 1 needs to be written to this register bit. 12 0 ro tx lpi indication 1 = indicates that the transmit pcs is currently receiving low power idle (lpi) signals. 0 = indicates that the pcs is not currently receiving low power idle (lpi) signals. this bit will dynamically indicate the presence of the tx lpi signa l. 11 0 ro/lh (latching high) rx lpi received 1 = indicates that the receive pcs has received low power idle (lpi) signaling one or more times since the register was last read. 0 = indicates that the pcs has not received low power idle (lpi) signaling. the status will be latched high and stay that way until cleared. to clear this stat us bit, a 1 needs to be written to this register bit. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 189 revision 1.0 port 1 eee control/status and auto?negotiation expansion r egister (0x0e4 C 0x0e5): p1eeecs (continued) bit default r/w description 10 0 ro rx lpi indication 1 = indicates that the receive pcs is currently receiving low power idle (lpi) signals. 0 = indicates that the pcs is not currently receiving low power idle (lpi) signals. this bit will dynamically indicate the presence of the rx lpi signal. 9C8 00 rw reserved 7 0 ro reserved 6 1 ro received next page location able 1 = received next page storag e location is specified by bit [6:5]. 0 = received next page storage location is not specified by bit [6:5]. 5 1 ro received next page storage location 1 = link partner next pages are stored in p1alprnp ( reg . 0x0de C 0x0df). 0 = link partner next pages are stored in p1anlpr (reg. 0x056 C 0x057). 4 0 ro/lh (latching high) parallel detection fault 1 = a fault h as been detected via the parallel d etection function. 0 = a fault has not been detected via the parallel detection function. this bit is cleared after read. 3 0 ro link partner next page able 1 = link partner is next page able d. 0 = link partner is not next page able d. 2 1 ro next page able 1 = local d evice is next page able d. 0 = local d evice is not next page able d. 1 0 ro/lh (latching high) page received 1 = a new page has been received . 0 = a new page has not been received . 0 0 ro link partner auto?negotiation able 1 = link p artner is auto ? negotiation abled. 0 = link p artner is not auto ? negotiation able d. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 190 revision 1.0 port 1 lpi recovery time counter register (0x0e6): p1lpirtc this register contains the port 1 lpi recovery time counter information . bit default value r/w description 7?0 0x27 (25s) rw port 1 lpi recovery time counter this register specifies the time that the mac device has to wait before it can start t o send out packets. this value should be the maximum of the lpi recovery time between local device and remote device. each count = 640ns. buffer load to lpi control 1 register (0x0e7): bl2lpic1 this register contains the buffer load to lpi control 1 information . bit default value r/w description 7 0 rw lpi terminated by input traffic enable 1 = lpi request will be stopped if input traffic is detected. 0 = lpi request wont be stopped by input traffic. 6 0 ro reserved 5?0 0x08 rw buffer load threshold for source port lpi termination this value defines the maximum buffer usage allowed for a single port before it starts to tr igger the lpi termination for the specific source port. (512 bytes per unit) port 2 auto?negotiation next page transmit register (0x0e8 C 0x0e9): p2anpt t his register contains the port 2 auto ? negotiation next p age t ransmit related bits . bit default r/w description 15 0 ro next page next p age (np) is used by the n ext p age function to indicate whether or not this is the last n ext p age to be transmitted. np shall be set as follows: 1 = a dditional n ext p age(s) will follow. 0 = l ast page. 14 0 ro reserved 13 1 ro message page message p age (mp) is used by the n ext p age function to differentiate a m essage p age from an u nformatted p age. mp shall be set as follows: 1 = message p age . 0 = unformatted p age . 12 0 ro acknowledge 2 ackno wledge 2 (ack2) is used by the next page function to indicate that a device has the ability to co mply with the message. ack2 shall be set as follows: 1 = able to comply with message. 0 = unable to comply with message. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 191 revision 1.0 port 2 auto?nego tiation next page transmit register (0x0e8 C 0x0e9): p2anpt (continued) bit default r/w description 11 0 ro toggle toggle (t) is used by the a rbitration function to e nsure synchronization with the link partner during n ext p age exchange. this bit shall always take the opposite value of the t oggle bit in the previously exchanged l ink c ode word. the initial value of the t oggle bit in the first n ext p age transmitted is the inverse of bit [ 11 ] in the base l ink c ode word and, therefore, may assume a value of logic one o r zero. the toggle bit shall be set as follows: 1 = p revious value of the transmitted l ink c ode word equal to logic zero. 0 = p revious value of the transmitted l ink c ode word equal to logic one. 10?0 0x00 1 rw message and unformatted code field message/unformatted code field bit [10:0] port 2 auto?negotiation link partner received next page register (0x0ea C 0x0eb): p2alprnp t his register contains the port 2 auto ? negotiation link partner received next p age related bits . bit default r/w description 15 0 ro next page next p age (np) is used by the n ext p age function to indicate whether or not this is the last n ext p age to be transmitted. np shall be set as follows: 1 = a dditional n ext p age(s) will follow. 0 = l ast page. 14 0 ro acknowledge acknowledge (ack) is used by the auto ? negotiation function to indicate that a device has successfully received its l ink p artners link code word. the acknowledge bit is encoded in bit 14 ] regardless of the value of the s elector f ield or l ink c ode word encoding. if no n ext p age information is to be sent, this bit shall be set to logic one in the l ink c ode word after the reception of at least three consecutive and consistent flp b ursts (ignoring the a cknowledge bit value). 13 0 ro message page message p age (mp) is used by the n ext p age function to differentiate a m essage p age from an u nformatted p age. mp shall be set as follows: 1 = message page . 0 = unformatted page . 12 0 ro acknowledge 2 ackno wledge 2 (ack2) is used by the next page function to indicate that a device has the ability to comply with the message. ack2 shall be set as follows: 1 = able to comply with message. 0 = unable to comply with message. 11 0 ro toggle toggle (t) is used by the arbitration function to e nsure synchronization with the link partner during n ext p age exchange. this bit shall always take the opposite value of the t oggle bit in the previously exchanged l ink c ode word. the initial value of the t oggle bit in the first n ext p age transmitted is the inverse of bit [ 11 ] in the base l ink c ode word and, therefore, may assume a value of logic one o r zero. the toggle bit shall be set as follows: 1 = p revious value of the transmitted l ink c ode word equal to logic zero. 0 = p revious va lue of the transmitted l ink c ode word equal to logic one. 10?0 0x000 ro message and unformatted code field message/ u nformatted code field bit [10:0] downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 192 revision 1.0 port 2 eee and link partner advertisement register (0x0ec C 0x0ed): p2eeea this register contains the port 2 eee advertisement and link partner advertisement information. note that eee is not supported in fiber mode . bit default r/w description 15 0 ro reserved 14 0 ro 10gbase?kr eee 1 = link partner eee is supported for 10gbase?kr. 0 = link partner eee is not supported for 10gbase?kr. 13 0 ro 10gbase?kx4 eee 1 = link partner eee is supported for 10gbase?kx4. 0 = link partner eee is not supported for 10gbase?kx4. 12 0 ro 1000base?kx eee 1 = link partner eee is supported for 1000base?kx. 0 = link partner eee is not supported for 1000base?kx. 11 0 ro 10gbase?t eee 1 = link partner eee is supported for 10gbase?t. 0 = link partner eee is not supported for 10gbase?t. 10 0 ro 1000base?t eee 1 = link partner eee is supported for 1000base?t. 0 = link partner eee is not supported for 1000base?t. 9 0 ro 100base?tx eee 1 = link partner eee is supported for 100base?tx. 0 = link partner eee is not supported for 100base?tx. 8C7 00 ro reserved 6 0 ro 10gbase?kr eee 1 = port 2 eee is supported for 10gbase?kr. 0 = port 2 eee is not supported for 10gbase?kr. 5 0 ro 10gbase?kx4 eee 1 = port 2 eee is supported for 10gbase?kx4. 0 = port 2 eee is not supported for 10gbase?kx4. 4 0 ro 1000base?kx eee 1 = port 2 eee is supported for 1000base?kx. 0 = port 2 eee is not supported for 1000base?kx. 3 0 ro 10gbase?t eee 1 = port 2 eee is supported for 10gbase?t. 0 = port 2 eee is not supported for 10gbase?t. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 193 revision 1.0 port 2 eee and link partner advertisement register (0x0ec C 0x0ed): p2eeea (continued) bit default r/w description 2 0 ro 1000base?t eee 1 = port 2 eee is supported for 1000base?t. 0 = port 2 eee is not supported for 1000base?t. 1 1 rw 100base?tx eee 1 = port 2 eee is supported for 100base?tx. 0 = port 2 eee is not supported for 100base?tx. to disable eee capability, clear the port 2 next page enable bit in the pcseeec register (0x0f3). 0 0 ro reserved port 2 eee wake error count register (0x0ee C 0x0ef): p2eeewec this register contains the port 2 eee wake error count information. note that eee is not supported in fiber mode. bit default value r/w description 15?0 0x0000 rw port 2 eee wake error count this counter is incremented by each transition of lpi_wake_timer_done from false to true. it means the wake - up time is longer than 20.5 s. the value will be held at all ones in the case of overflow and will be cleared to zero after this register is read. port 2 eee control/status and auto?negotiation expansion register (0x0f0 C 0x0f1): p2eeecs this register contains the port 2 eee control/status and auto ? negotiation expansion information. note that eee is not supported in fiber mode. bit default r/w description 15 1 rw reserved 14 0 ro hardware 100bt eee enable status 1 = 100bt eee is enabled by hardware based np exchange . 0 = 100bt eee is disabled . 13 0 ro/lh (latching high) tx lpi received 1 = indicates that the transmit pcs has received low power idle (lpi) signaling one or more times since the register was last read. 0 = indicates that the pcs has not received low power idle (lpi) signaling. the status will be latched high and stay that way until cleared. to clear this stat us bit, a 1 needs to be written to this register bit. 12 0 ro tx lpi indication 1 = indicates that the transmit pcs is currently receiving low power idle (lpi) signals. 0 = indicates that the pcs is not currently receiving low power idle (lpi) signals. this bit will dynamically indicate the presence of the tx lpi signal. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 194 revision 1.0 port 2 eee control/status and auto?negotiation expansion register (0x0 f0 C 0x0f1): p2eeecs (continued) bit default r/w description 11 0 ro/lh (latching high) rx lpi received 1 = indicates that the receive pcs has received low power idle (lpi) signaling one or more times since the register was last read. 0 = indicates that the pcs has not received low power idle (lpi) signaling. the status will be latched high and stay that way until cleared. to clear this stat us bit, a 1 needs to be written to this register b it. 10 0 ro rx lpi indication 1 = indicates that the receive pcs is currently receiving low power idle (lpi) signals. 0 = indicates that the pcs is not currently receiving low power idle (lpi) signals. this bit will dynamically indicate the presence of the rx lpi signal. 9C8 00 rw reserved 7 0 ro reserved 6 1 ro received next page location able 1 = received n ext p age storage location is specified by bits[ 6:5]. 0 = received n ext p age storage location is not specified by bits[ 6:5]. 5 1 ro received next page storage location 1 = link p artner n ext p ages are stored in p2alprnp (reg. 0x0ea C 0x0eb). 0 = link p artner n ext p ages are stored in p2anlpr (reg. 0x062 C 0x063). 4 0 ro/lh (latching high) parallel detection fault 1 = a fault h as been detected via the parallel d etection function. 0 = a fault has not been detected via the parallel detection function. this bit is cleared after read. 3 0 ro link partner next page able 1 = link p artner is n ext p age able d. 0 = link p artner is not n ext p age able d. 2 1 ro next page able 1 = local device is n ext p age able d. 0 = local device is not n ext p age able d. 1 0 ro/lh (latching high) page received 1 = a n ew p age has been received . 0 = a n ew p age has not been received . 0 0 ro link partner auto?negotiation able 1 = link p artner is auto ? negotiation abled. 0 = link p artner is not auto ? negotiation able d. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 195 revision 1.0 port 2 lpi recovery time counter register (0x0f2): p2lpirtc t his register contains the port 2 lpi recovery time counter information . bit default value r/w description 7?0 0x27 (25s) rw port 2 lpi recovery time counter this register specifies the time that the mac device has to wait before it can start t o send out packets. this value should be the maximum of the lpi recovery time between local device and remote device. each count = 640ns. pcs eee control register (0x0f3): pcseeec this register contains the pcs eee control information. bit default r/w description 7-6 00 rw reserved 5?2 0x0 ro reserved 1 1 rw port 2 next page enable 1 = enable next page exchange during auto ? negotiation . 0 = skip next page exchange during auto ? negotiation . auto- negotiation uses next page to negotiate eee. to disable eee auto - negotiation on port 2, clear this bit to zero. restarting auto - negotiation may then be required. 0 1 rw port 1 next page enable 1 = enable next page exchange during auto ? negotiation . 0 = skip next page exchange during auto ? negotiation . auto- negotiation uses next page to negotiate eee. to disable eee auto - negotiation on port 1, clear this bit to zero. restarting auto - negotiation may then be required. empty txq to lpi wait time control register (0x0f4 C 0x0f5): etlwtc t his register contains the empty txq to lpi wait time control information . bit default value r/w description 15?0 0x03e8 rw empty txq to lpi wait time control this register specifies the time that the lpi request will be generated after a txq has been empty exceeds this configured time. this is only valid when eee 100bt is enabled. this setting will apply to all the three ports. the unit is 1.3 ms. the default value is 1.3 sec. ( in a range from 1.3ms to 86 second s) downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 196 revision 1.0 buffer load to lpi control 2 register (0x0f6 C 0x0f7): bl2lpic2 this register contains the buffer load to lpi control 2 information . bit default value r/w description 15?8 0x00 ro reserved 7?0 0x40 rw buffer load threshold for all ports lpi termination this value defines the maximum buffer usage allowed for a single port before it starts to tr igger the lpi termination for every port. (128 bytes per unit) 0x0f8 C 0x0ff: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 197 revision 1.0 internal i/o register space mapping for interrupts, biu, and global reset (0x100 C 0x1ff) 0x100 C 0x107 : reserved chip configuration register (0x108 C 0x109): ccr this register indicates the chip configuration mode based on strapping and bonding options. bit default value r/w description 15?11 ? ro reserved 10 ? ro bus endian m ode the p2led0/lebe pin value is latched into this bit during power?up/reset . 0 = bus in big endian mode 1 = bus in little endian mode 9 ? ro eeprom p resence the pme/eeprom pin value is latched into this bit during power?up/reset . 0 = no external eeprom 1 = use external eeprom 8 0 ro reserved 7 ? ro 8?bit data bus width this bit value is loaded from p1led0/h816 (pin 60) to indicate the data bus mode. 0 = not in 8?bit bus mode operation 1 = in 8?bit b us mode operation 6 ? ro 16?bit data bus width this bit value is loaded from p1led0/h816 (pin 60) to indicate the data bus mode. 0 = n ot in 16?bit bus mode operation 1 = in 16?bit bus mode operation 5 0 ro reserved 4 1 ro shared data bus mode for d ata and address 0 = not valid 1 = data and address bus are shared. 3C0 0 x2 ro reserved 0x10a C 0x10f: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 198 revision 1.0 host mac address registers: marl, marm and marh these host mac address registers are loaded starting at word location 0x1 of the eeprom upon hardwa re reset. the software driver can read or write these registers values, but it will not modify the original host mac address values in the eeprom. these six bytes of host mac address in external eeprom are loaded to these three registers as mapped below: ? marl[15:0] = eeprom 0x1(mac byte 2 and 1) ? marm[15:0] = eeprom 0x2(mac byte 4 and 3) ? marh[15:0] = eeprom 0x3(mac byte 6 and 5) the host mac address is used to define the individual destination address that the ksz8462 responds to when receivi ng frames. network addresses are generally expressed in the form of 01:23:45:67:89:ab, where the bytes are received from left to right, and the bits within each byte are received from right to left (lsb to msb). for example, the actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101. these three registers value for host mac address 01:23:45:67:89:ab will be held as below : ? marl[15:0] = 0x89ab ? marm[15:0] = 0x4567 ? marh[15:0] = 0x0123 host mac address register low (0x110 C 0x111): marl r egister bit fields for the low word of the host mac address . bit default value r/w description 15?0 ? rw marl mac address low the least significant word of the mac address. host mac address register middle (0x112 C 0x113): marm the following table shows the register bit fields for the middle word of the host mac address . bit default value r/w description 15?0 ? rw marm mac address middle the middle word of the mac address. host mac address register high (0x114 C 0x115): marh the following table shows the register bit fields for the high word of the host mac addr ess. bit default value r/w description 15?0 ? rw marh mac address high the most significant word of the mac address. 0x116 C 0x121: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 199 revision 1.0 eeprom control register (0x122 C 0x123): eepcr to support an external eeprom, the pme/eeprom pin should be pulled?up to high ; otherwise, it should be pulled?down to low . if an external eeprom is not used, the software should program the host mac address . if an eeprom is used in the design, the chip host mac address can be loaded from the eeprom immediately after reset. the ksz8462 allows the software to access (read or write) the eeprom directly; that is, the ee prom access timing can be fully controlled by the software if the eeprom software access bit is set. bit default value r/w description 15?6 ? ro reserved 5 0 wo eesrwa eeprom software read or write access 0 = s/w read enable to access eeprom when software access enabled (bit[4] = 1) 1 = s/w write enable to access eeprom when software access enabled (bit[4] = 1) 4 0 rw eesa eeprom software access 1 = enable software to access eeprom through bits[ 3:0]. 0 = disa ble software to access eeprom. 3 ? ro eesb eeprom status bit data receive from eeprom. this bit directly reads the eedio pin. 2 0 rw eecb_eeprom_wr_data write data to eeprom. this bit directly controls the devices eedio pin. 1 0 rw eecb_eeprom_clock serial eeprom clock. this bit directly controls the devices eesk pin. 0 0 rw eecb_eeprom_cs chip select for the eeprom. this bit directly controls the devices eecs pin . memory bist info register (0x124 C 0x125): mbir this register indicates the built?in self - test results for both tx and rx memories after power?up/reset. the device shoul d be reset after the bist procedure to ensure proper subsequent operation. bit default value r/w description 15 0 ro memory bist done 0 = bist in progress 1 = bist done 14?13 00 ro reserved 12 ? ro txmbf tx memory bist completed 0 = tx memory built - in self - test has not completed. 1 = tx memory built - in self - test has completed. 11 ? ro txmbfa tx memory bist failed 0 = tx memory built - in self - test has completed without failure. 1 = tx memory built - in self - test has completed with failure. 10?8 ? ro txmbfc tx memory bist fail count 0 = tx memory built - in self test completed with no count failure. 1 = tx memory built - in self test encountered a failed count condition. 7?5 ? ro reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 200 revision 1.0 memory bist info register (0x124 C 0x125): mbir (continued) bit default value r/w description 4 ? ro rxmbf rx memory bist completed 0 = completion has not occurred for the memory built - in self - test 1 = indicates completion of the rx memory built ? in self - test . 3 ? ro rxmbfa rx memory bist failed 0 = no failure with the rx memory built - in self - test . 1 = indicates the rx memory built - in self - test has failed. 2?0 ? ro rxmbfc rx memory bist test fail count 0 = no count failure for the rx memory bist 1 = indicates the rx memory built - in self - test failed count. global reset register (0x126 C 0x127): grr this register controls the global and ptp reset functions with information programmed by the cpu. bit default value r/w description 15?4 0x000 rw reserved . 3 0 rw memory bist start 1 = setting this bit will start the memory bist . 0 = setting this bit will stop the memory bist. 2 0 rw ptp module soft reset 1 = setting this bit resets the 1588/ptp blocks including the timestamp input units, the trigger output units and the ptp clock. 0 = software reset is inactive. 1 0 rw qmu module soft reset 1 = software reset is active to clear both the txq and rxq memories. 0 = qmu reset is inactive. qmu software reset will flush out all tx/rx packet data inside the txq and rxq memories and reset all the qmu registers to their default value. 0 0 rw global soft reset 1 = software reset is active. 0 = software reset is inactive. global software reset will reset all registers to their default value. the strap?in values are not affected. this bit is not self - clearing . after writing a 1 to this bit , wait for 10 m s to elapse then write a 0 for normal operation. 0x128 C 0x129 : reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 201 revision 1.0 wake - up frame control register (0x12a C 0x12b): wfcr this register holds control information programmed by the cpu to control the wake - up frame function. bit default value r/w description 15?8 0x00 ro reserved 7 0 rw mprxe magic packet rx enable when set, it enables the magic packet pattern detection. when reset, the magic packet pattern detection is disabled. 6?4 000 ro reserved 3 0 rw wf3e wake - up frame 3 enable when set, it enables the wake - up frame 3 pattern detection. when reset, the wake - up frame 3 pattern detection is disabled. 2 0 rw wf2e wake - up frame 2 enable when set, it enables the wake - up frame 2 pattern detection. when reset, the wake - up frame 2 pattern detection is disabled. 1 0 rw wf1e wake - up frame 1 enable when set, it enables the wake - up frame 1 pattern detection. when reset, the wake - up frame 1 pattern detection is disabled. 0 0 rw wf0e wake - up frame 0 enable when set, it enables the wake - up frame 0 pattern detection. when reset, the wake - up frame 0 pattern detection is disabled. 0x12c C 0x12f: reserved wake - up frame 0 crc0 register (0x130 C 0x131): wf0crc0 this register contains the expected crc values of the wake - up frame 0 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard; it is taken over the bytes spec ified in the wake - up byte mask registers. bit default value r/w description 15?0 0x0000 rw wf0crc0 wake - up frame 0 crc (lower 16 bits) the expected crc value of a wake - up frame 0 pattern. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 202 revision 1.0 wake - up frame 0 crc1 register (0x132 C 0x133): wf0crc1 this register contains the expected crc values of the wake - up frame 0 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard; it is taken over the bytes spec ified in the wake - up byte mask registers. bit default value r/w description 15?0 0x0000 rw wf0crc1 wake - up frame 0 crc (upper 16 bits). the expected crc value of a wake - up frame 0 pattern. wake - up frame 0 byte mask 0 register (0x134 C 0x135): wf0bm0 this register contains the first 16 bytes mask values of the wake - up frame 0 pattern. setting bit [0] selects the first byte of the wake - up frame 0. setting bit [15] selects the 16th byte of the wake - up frame 0. bit default value r/w description 15?0 0x0000 rw wf0bm0 wake - up frame 0 byte mask 0 the first 16 byte mask of a wake - up frame 0 pattern. wake - up frame 0 byte mask 1 register (0x136 C 0x137): wf0bm1 this register contains the next 16 bytes mask values of the wake - up frame 0 pattern. setting bit [0] selects the 17th byte of the wake - up frame 0. setting bit [15] selects the 32nd byte of the wake - up frame 0. bit default value r/w description 15?0 0x0000 rw wf0bm1 wake - up frame 0 byte mask 1. the next 16 byte mask covering bytes 17 to 32 of a wake - up frame 0 pattern. wake - up frame 0 byte mask 2 register (0x138 C 0x139): wf0bm2 this register contains the next 16 bytes mask values of the wake - up frame 0 pattern. setting bit [0] selects the 33rd byte of the wake - up frame 0. setting bit [15] selects the 48th byte of the wake - up frame 0. bit default value r/w description 15?0 0x0000 rw wf0bm2 wake?up frame 0 byte mask 2. the next 16 byte mask covering bytes 33 to 48 of a wake?up frame 0 pattern. wake - up frame 0 byte mask 3 register (0x13a C 0x13b): wf0bm3 this register contains the last 16 bytes mask values of the wake - up fra me 0 pattern. setting bit [0] selects the 49th byte of the wake - up frame 0. setting bit [15] selects the 64th byte of the wake - up frame 0. bit default value r/w description 15?0 0x0000 rw wf0bm3 wake?up frame 0 byte mask 3. the last 16 byte mask covering bytes 49 to 64 of a wake?up frame 0 pattern. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 203 revision 1.0 0x13c C 0x13f: reserved wake - up frame 1 crc0 register (0x140 C 0x141): wf1crc0 this register contains the expected crc values of the wake - up frame 1 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard; it is taken over the bytes spec ified in the wake - up byte mask registers. bit default value r/w description 15?0 0x0000 rw wf1crc0 wake?up frame 1 crc (lower 16 bits). the expected crc values of a wake?up frame 1 pattern. wake - up frame 1 crc1 register (0x142 C 0x143): wf1crc1 this register contains the expected crc values of the wake - up frame 1 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes spec ified in the wake - up byte mask registers. bit default value r/w description 15?0 0x0000 rw wf1crc1 wake?up frame 1 crc (upper 16 bits). the expected crc value of a wake?up frame 1 pattern. wake - up frame 1 byte mask 0 register (0x144 C 0x145): wf1bm0 this register contains the first 16 bytes mask values of the wake - up frame 1 pattern. setting bit [0] selects the first byte of the wake - up frame 1, setting bit [15] selects the 16th byte of the wake -up frame 1. bit default value r/w description 15?0 0x0000 rw wf1bm0 wake?up frame 1 byte mask 0. the first 16 byte mask of a wake?up frame 1 pattern. wake - up frame 1 byte mask 1 register (0x146 C 0x147): wf1bm1 this register contains the next 16 bytes mask values of the wake - up frame 1 pattern. setting bit [0] selects the 17th byte of the wake - up frame 1. setting bit [15] selects the 32nd byte of the wake - up frame 1. bit default value r/w description 15?0 0x0000 rw wf1bm1 wake - up frame 1 byte mask 1. the next 16 byte mask covering bytes 17 to 32 of a wake?up frame 1 pattern. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 204 revision 1.0 wake - up frame 1 byte mask 2 register (0x148 C 0x149): wf1bm2 this register contains the next 16 bytes mask values of the wake - up frame 1 pattern. setting bit [0] selects the 33rd byte of the wake - up frame 1. setting bit [15] selects the 48th byte of the wake - up frame 1. bit default value r/w description 15?0 0x0000 rw wf1bm2 wake?up frame 1 byte mask 2. the next 16 bytes mask covering bytes 33 to 48 of a wake?up frame 1 pattern. wake - up frame 1 byte mask 3 register (0x14a C 0x14b): wf1bm3 this register contains the last 16 bytes mask values of the wake - up frame 1 pattern. setting bit 0 selects the 49th byte of the wake - up frame 1. setting bit 15 selects the 64th byte of the wake - up frame 1. bit default value r/w description 15?0 0x0000 rw wf1bm3 wake?up frame 1 byte mask 3. the last 16 bytes mask covering bytes 49 to 64 of a wake?up frame 1 pattern. 0x14c C 0x14f: reserved wake - up frame 2 crc0 register (0x150 C 0x151): wf2crc0 this register contains the expected crc values of the wake - up frame 2 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes speci fied in the wake - up byte mask registers. bit default value r/w description 15?0 0x0000 rw wf2crc0 wake?up frame 2 crc (lower 16 bits). the expected crc value of a wake?up frame 2 pattern. wake - up frame 2 crc1 register (0x152 C 0x153): wf2crc1 this register contains the expected crc values of the wake?up frame 2 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes spec ified in the wake - up byte mask registers. bit default value r/w description 15?0 0x0000 rw wf2crc1 wake?up frame 2 crc (upper 16 bits). the expected crc value of a wake?up frame 2 pattern. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 205 revision 1.0 wake - up frame 2 byte mask 0 register (0x154 C 0x155): wf2bm0 this register contains the first 16 bytes mask values of the wake - up frame 2 pattern. setting bit [0] selects the first byte of the wake - up frame 2, setting bit [15] selects the 16th byte of the wake - up frame 2. bit default value r/w description 15?0 0x0000 rw wf2bm0 wake?up frame 2 byte mask 0. the first 16 byte mask of a wake?up frame 2 pattern. wake - up frame 2 byte mask 1 register (0x156 C 0x157): wf2bm1 this register contains the next 16 bytes mask values of the wake - up frame 2 pattern. setting bit [0] selects the 17th byte of the wake - up frame 2. setting bit [15] selects the 32nd byte of the wake - up frame 2. bit default value r/w description 15?0 0x0000 rw wf2bm1 wake?u p frame 2 byte mask 1. the next 16 byte mask covering bytes 17 to 32 of a w ake?up frame 2 pattern. wake - up frame 2 byte mask 2 register (0x158 C 0x159): wf2bm2 this register contains the next 16 bytes mask values of the wake - up frame 2 pattern. setting bit [0] selects the 33rd byte of the wake - up frame 2. setting bit [15] selects the 48th byte of the wake - up frame 2. bit default value r/w description 15?0 0 x0000 rw wf2bm2 wake?up frame 2 byte mask 2. the next 16 byte mask covering bytes 33 to 48 of a wake?up frame 2 pattern. wake - up frame 2 byte mask 3 register (0x15a C 0x15b): wf2bm3 this register contains the last 16 bytes mask values of the wake - up fra me 2 pattern. setting bit [0] selects the 49th byte of the wake - up frame 2. setting bit [15] selects the 64th byte of the wake - up frame 2. bit default value r/w description 15?0 0 x0000 rw wf2bm3 wake?up frame 2 byte mask 3. the last 16 byte mask covering bytes 49 t o 64 of a wake?up frame 2 pattern. 0x15c C 0x15f: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 206 revision 1.0 wake - up frame 3 crc0 register (0x160 C 0x161): wf3crc0 this register contains the expected crc values of the wake - up frame 3 pattern. the value of the crc calculated is based on the ieee 802.3 ethernet standard, it is taken over the bytes specified in the wake?up byte mask registers. wake - up frame 3 crc1 register (0x162 C 0x163): wf3crc1 this register contains the expected crc values of the wake - up frame 3 pattern. the value of the crc calculate d is based on the ieee 802.3 ethernet standard, it is taken over the bytes specified in the wake?up byte mask registers. bit default value r/w description 15?0 0 x0000 rw wf3crc1 wake?up frame 3 crc (upper 16 bits). the expected crc value of a wake - up frame 3 pattern. wake - up frame 3 byte mask 0 register (0x164 C 0x165): wf3bm0 this register contains the first 16 bytes mask values of the wake - up frame 3 pattern. setting bit [0] selects the first byte of the wake - up frame 3, setting bit [15] selects the 16th byte of the wake - up frame 3. bit default value r/w description 15?0 0 x0000 rw wf3bm0 wake - up frame 3 byte mask 0. the first 16 byte mask of a wake - up frame 3 pattern. wake - up frame 3 byte mask 1 register (0x166 C 0x167): wf3bm1 this register contains the next 16 bytes mask values of the wake - up frame 3 pattern. setting bit [0] selects the 17th byte of the wake - up frame 3. setting bit [15] selects the 32nd byte of the wake - up frame 3. bit default value r/w description 15?0 0 x0000 rw wf3bm1 wake - up frame 3 byte mask 1. the next 16 byte mask covering bytes 17 to 32 of a wake - up frame 3 pattern. wake - up frame 3 byte mask 2 register (0x168 C 0x169): wf3bm2 this register contains the next 16 bytes mask values of the wake - up frame 3 pattern. setting bit [0] selects the 33rd byte of the wake - up frame 3. setting bit [15] selects the 48th byte of the wake - up frame 3. bit default value r/w description 15?0 0 x0000 rw wf3bm2 wake - up frame 3 byte mask 2. the next 16 byte mask covering bytes 33 to 48 of a wake - up frame 3 pattern. bit default value r/w description 15?0 0 x0000 rw wf3crc0 wake?up frame 3 crc (lower 16 bits). the expected crc value of a wake - up frame 3 pattern. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 207 revision 1.0 wake - up frame 3 byte mask 3 register (0x16a C 0x16b): wf3bm3 this register contains the last 16 bytes mask values of the wake - up frame 3 pattern. setting bit [0] selects the 49th byte of the wake - up frame 3. setting bit [15] selects the 64th byte of the wake - up frame 3. bit default value r/w description 15?0 0 x0000 rw wf3bm3 wake - up frame 3 byte mask 3. the last 16 byte mask covering bytes 49 to 64 of a wake - up frame 3 pattern. 0x16c C 0x16f: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 208 revision 1.0 internal i/o register space mapping for the queue management unit (qmu) (0x170 C 0x1ff) transmit control register (0x170 C 0x171): txcr this register holds control information programmed by the cpu to control the qmu transmit m odule function. bit default value r/w description 15?9 ? ro reserved . 8 0 rw tcgicmp transmit checksum generation for icmp when this bit is set, the device hardware is enabled to generate an icmp frame checksum in a non - fragmented icmp frame. 7 0 rw tcgudp transmit checksum generation for udp when this bit is set, the device hardware is enabled to generate a upd frame checks um in a non - fragmented udp frame. 6 0 rw tcgtcp transmit checksum generation for tcp when this bit is set, the device hardware is enabled to generate a tcp frame checksum in a non - fragmented tcp frame. 5 0 rw tcgip transmit checksum generation for ip when this bit is set, the device hardware is enabled to generate an ip header checksum in a non - fragmented ip frame. 4 0 rw ftxq flush transmit queue when this bit is set, the transmit queue memory is cleared and tx frame pointer is reset . note: disable the txe transmit enable bit[0] first before set ting this bit, then clear this bit to normal operation. 3 0 rw txfce transmit flow control enable when this bit is set and the device is in full?duplex mode, flow contr ol is enabled. the device transmits a pause frame when the receive buffer capacity reaches a threshold level that will cause the buffer to overflow. when this bit is set and the device is in half?duplex mode, back?pr essure flow control is enabled. when this bit is cleared, no transmit flow control is enabled. 2 0 rw txpe transmit padding enable when this bit is set, the device automatically adds a padding field to a packet shorter than 64 bytes. note: setting this bit requires enabling the add crc feature (bit[1] = 1) to avoid crc er rors for the transmit packet. 1 0 rw txce transmit crc enable when this bit is set, the device automatically adds a 32?bit crc che cksum field to the end of a transmit frame. 0 0 rw txe transmit enable when this bit is set, the transmit module is enabled and placed in a running state. when reset, the transmit process is placed in the stopped state after the transmission of the current fr ame is completed. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 209 revision 1.0 transmit status register (0x172 C 0x173): txsr this register keeps the status of the last transmitted frame in the qmu transmit module . bit default value r/w description 15?14 00 ro reserved 13 0 ro txlc transmit late collision this bit is set when a transmit late collision occurs. 12 0 ro txmc transmit maximum collision this bit is set when a transmit maximum collision is reached. 11?6 ? ro reserved 5?0 ? ro txfid transmit frame id this field identifies the transmitted frame. all of the transmit status informati on in this register belongs to the frame with this id. receive control register 1 (0x174 C 0x175): rxcr1 this register holds control information programmed by the host to control the receive function in the qmu module . bit default value r/w description 15 0 rw frxq flush receive queue when this bit is set, the receive queue memory is cleared and rx frame pointer is reset. note: disable the rxe receive enable bit[0] first before setting this bit, then c lear this bit for normal operation. 14 0 rw rxudpfcc receive udp frame checksum check enable while this bit is set, if any received udp frame has an incorrect udp checksum, the frame will be discarded. 13 0 rw rxtcpfcc receive tcp frame checksum check enable while this bit is set, if any received tcp frame has an incorrect tcp check sum, the frame will be discarded. 12 0 rw rxipfcc receive ip frame checksum check enable while this bit is set, if any received ip frame has an incorrect ip checks um, the frame will be discarded. 11 1 rw rxpafma receive physical address filtering with mac address enable this bit enables the rx function to receive the physical address that passes the mac addr ess filtering mechanism (see mac address filtering scheme in table 2 for details). 10 0 rw rxfce receive flow control enable when this bit is set and the device is in full?duplex mode, flow control is enabled, and the device will acknowledge a pause frame from the receive interface; i.e., the outgoing packet s are pending in the transmit buffer until the pause frame control timer expires. this field ha s no meaning in half?duplex mode and should be progr ammed to 0. when this bit is cleared, flow control is not enabled. 9 0 rw rxefe receive error frame enable when this bit is set, frames with crc error are allowed to be received into the rx queue. when this bit is cleared, all crc error frames are discarded. 8 0 rw rxmafma receive multicast address filtering with mac address enable when this bit is set, this bit enables the rx function to receive multicast addres s that pass the mac address filtering mechanism (see mac address filtering scheme in table 2 for details). downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 210 revision 1.0 receive control register 1 (0x174 C 0x175): rxcr1 (continued) bit default value r/w description 7 0 rw rxbe receive broadcast enable when this bit is set, the rx module is enabled to receive all the broadcast frames. 6 0 rw rxme receive multicast enable when this bit is set, the rx module is enabled to receive all the multicast frames (inc luding broadcast frames). 5 0 rw rxue receive unicast enable when this bit is set, the rx module is enabled to receive unicast frames that match the 48?bit station mac address of the module. 4 0 rw rxae receive all enable when this bit is set, the device is enabled to receive all incoming frames, regar dless of the frames destination address (see mac address filtering scheme in table 2 for d etails). 3C2 00 rw reserved 1 0 rw rxinvf receive inverse filtering when this bit is set, the device receives function with address check operation in invers e filtering mode (see mac address filtering scheme in table 2 for details). 0 0 rw rxe receive enable when this bit is set, the rx block is enabled and placed in a running state. when this bit is cleared, the receive process is placed in the stopped state upon completi ng reception of the current frame. receive control register 2 (0x176 C 0x177): rxcr2 this register holds control information programmed by the host to control the receive function in the qmu module . bit default value r/w description 15?9 ? ro reserved 8 1 rw eqfcpt enable qmu flow control pause timer wh ile this bit is set, another pause frame will be sent out if the pause timer is expired and rxq (12kb) is still above the low water mark. the pause timer will reset itself when it expires and rxq is still above the low water mark and it will be disabled or stop co unting when rxq is below the low water mark. the pause frame is sent out before rxq i s above the high water mark. 7?5 000 ro reserved 4 1 rw iuffp ipv4/ipv6/udp fragment frame pass while this bit is set, the device will pass the frame without checking the udp checksum at the received side for ipv6 udp frames with a fragmented extension header. operating with this bit cleared is not a valid mode since the hardware cannot calculate a correct udp checks um without all of the ip fragments. 3 0 rw reserved 2 1 rw udplfe udp lite frame enable while this bit is set, the ksz8462 will check the checksum at receive side and generat e the checksum at transmit side for udp lite frame. while this bit is cleared, the ksz8462 will pass the checksum check at receive side and skip the checksum generation at transmit side for udp lite frame . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 211 revision 1.0 receive control register 2 (0x176 C 0x177): rxcr2 (continued) bit default value r/w description 1 0 rw rxicmpfcc receive icmp frame checksum check enable while this bit is set, any received icmp frame (only a non?fragmente d frame) with an incorrect checksum will be discarded. if this bit is not set, the frame will not be discarde d even though there is an ic mp checksum error. 0 0 rw rxsaf receive source address filtering while this bit is set, the device will drop the frame if the source address is the same as the mac address in the marl, marm, marh registers. txq memory information register (0x178 C 0x179): txmir this register indicates the amount of free memory available in the txq of the qmu module. bit default value r/w description 15?13 ? ro reserved . 12?0 0x1800 ro txma transmit memory available the amount of memory available is represented in units of byte. the txq memory is used for both frame payload, control word. note: software must be written to ensure that there is enough memory for the next transmi t frame including control information before transmit data is written to the txq. 0 x17a C 0x17b: reserved receive frame header status register (0x17c C 0x17d): rxfhsr this register indicates the received frame header status information . t he received frames are reported in the rxfc register. this register contains the status information for the frame received , and the host processor can read as many times as the frame count value in the rxfc register . bit default value r/w description 15 ? ro rxfv receive frame valid this bit is set if the present frame in the receive packet memory is valid. the status information currently in this location is also valid. when clear, it indicates that there is either no pending receive frame or that the curr ent frame is still in the process of receiving. 14 ? ro reserved 13 ? ro rxicmpfcs receive icmp frame checksum status when this bit is set, the ksz8462 received icmp frame checksum is incorrect . 12 ? ro rxipfcs receive ip frame checksum status when this bit is set, the ksz8462 received ip header checksum is incorrect. 11 ? ro rxtcpfcs receive tcp frame checksum status when this bit is set, the ksz8462 received tcp frame checksum is incorrect. 10 ? ro rxudpfcs receive udp frame checksum status when this bit is set, the ksz8462 received udp frame checksum is incorrect. 9?8 ? ro reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 212 revision 1.0 receive frame header status register (0x17c C 0x17d): rxfhsr (continued) bit default value r/w description 7 ? ro rxbf receive broadcast frame when this bit is set, it indicates that this frame has a broadcast address. 6 ? ro rxmf receive multicast frame when this bit is set, it indicates that this frame has a multicast address (i ncluding the broadcast address). 5 ? ro rxuf receive unicast frame when this bit is set, it indicates that this frame has a unicast address. 4 ? ro reserved 3 ? ro rxft receive frame type when this bit is set, it indicates that the frame is an ethernet?type fram e (frame length is greater than 1500 bytes). when clear, it indicates that the frame is an ieee 802.3 frame. this bit is not valid for runt frames. 2 ? ro reserved 1 ? ro rxrf receive runt frame when this bit is set, it indicates that a frame was damaged by a collision or had a prematur e termination before the collision window passed. runt frames are passed to the host only if the pass bad frame bit is set. 0 ? ro rxce receive crc error when this bit is set, it indicates that a crc error has occurred on the current recei ved frame. crc error frames are passed to the host only if the pass bad frame bit is set. receive frame header byte count register (0x17e C 0x17f): rxfhbcr this register indicates the received frame header byte count information. the received frames are reported in the rxfc register. this register contains the total number of bytes information for the frame received , and the host processor can read as many times as the frame count value in the rxfc register . bit default value r/w description 15?12 ? ro reserved 11?0 ? ro rxbc receive byte count this field indicates the present received frame byte size. note: always read low byte first for 8?bit mode operation . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 213 revision 1.0 txq command register (0x180 C 0x181): txqcr this register is programmed by the host cpu to issue a transmit command to the txq . the present transmit frame in the txq memory is queued for transmit. bit default value r/w description 15?3 ? rw reserved 2 0 rw reserved 1 0 rw txqmam txq memory available monitor when this bit is written as a 1, the ksz8462 will generate interrupt (bit [6] in the isr r egister) to the cpu when txq memory is available based upon the total amount of txq space requested by cp u at txntfsr (0x19e) register. note : this bit is self?clearing after the frame is finished transmitt ing. the software should wait for the bit to be cleared before setting to 1 again. 0 0 rw metfe manual enqueue txq frame enable when this bit is written as 1, the ksz8462 will enable the current tx frame in the tx buffer to be queued for transmit one frame at a time. note : this bit is self?cleared after the frame transmission is comple te . the software should wait for the bit to be cleared before setting up another new tx frame. rxq command register (0x182 C 0x183): rxqcr this register is programmed by the host cpu to issue dma read or writ e command to the rxq and txq. this register also is used to control all rx thresholds enable and status. bit default value r/w description 15?13 ? rw reserved 12 ? ro rxdtts rx duration timer threshold status when this bit is set, it indicates that rx interrupt is due to the time starting at t he first received frame in the rxq buffer exceeding the threshold set in the rx duration timer threshold register (0x18c, rxdttr). this bit will be updated when a 1 is written to bit [13] in the isr register. 11 ? ro rxdbcts rx data byte count threshold status when this bit is set, it indicates that the rx interrupt is due to the number of received bytes in rxq buffer exceeding the threshold set in the rx data byte count threshold register (0x18e, rxdbctr). this bit will be updated when a 1 is written to bit [13] in the isr register. 10 ? ro rxfcts rx frame count threshold status when this bit is set, it indicates that the rx interrupt is due to the number of received frames in rxq buffer exceeding the threshold set in the rx frame count threshold register (0x19c, rxfctr). this bit will be updated when a 1 is written to bit [13] in the isr register. 9 0 rw rxiphtoe rx ip header two?byte offset enable when this bit is written as 1, the device will enable the adding of two bytes before the frame header in order for the ip header inside the frame contents to be aligned with a double word boundary to speed up software operation. 8 ? rw reserved 7 0 rw rxdtte rx duration timer threshold enable when this bit is written as 1, the device will enable the rx interrupt (bit [13] in the isr) when the time starts at the first received frame in the rxq buffer if it exceeds the thre shold set in the rx duration timer threshold register (0x18c, rxdttr). downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 214 revision 1.0 rxq command register (0x182 C 0x183): rxqcr (continued) bit de fault value r/w description 6 0 rw rxdbcte rx data byte count threshold enable when this bit is written as 1, the device will enable the rx interrupt (bit [13] in is r) when the number of received bytes in the rxq buffer exceeds the threshold set in the rx data byte count threshold register (0x18e, rxdbctr). 5 0 rw rxfcte rx frame count threshold enable when this bit is written as 1, the device will enable the rx interrupt (bit [13] in is r) when the number of received frames in the rxq buffer exceeds the threshold set in the rx frame count threshold register (0x19c, rxfctr). 4 0 rw adrfe auto?dequeue rxq frame enable when this bit is written as 1, the device will automatically enable rxq frame buffer dequeue. the read pointer in the rxq frame buffer will be automatically adjusted to the next received frame location after the current frame is completely read by the host. 3 0 rw sda start dma access when this bit is written as 1, the device allows a dma operation from the host cpu to access either the read rxq frame buffer or the write txq frame buffer with csn and rdn or wrn signals while the cmd pin is low. all register accesses are disabled except for access to this register during this dma operation. this bit must be set to 0 when the dma operation is finished in order to access the rest of the registers. 2?1 ? rw reserved 0 0 rw rrxef release rx error frame when this bit is written as 1, the current rx error frame buffer is released. note: this bit is self?cleared after the frame memory is released. t he software should wait for the bit to be cleared before processing a new rx frame. tx frame data pointer register (0x184 C 0x185): txfdpr the value of this register determines the address to be accessed within the txq frame buffer. when the auto inc rement is set, it will automatically increment the pointer value on write accesses to the data regist er. the counter is incremented by one for every byte access, by two for every word access, and by four for every double word access. bit default value r/w description 15 ? ro reserved 14 0 rw txfpai tx frame data pointer auto increment 1: when this bit is set, the tx frame data pointer register increments automaticall y on accesses to the data register. the increment is by one for every byte access, by two for every word access, and by four for every double word access. 0: when this bit is reset, the tx frame data pointer is manually controlled by the user t o access the tx frame location. 13?11 ? ro reserved 10?0 0x000 ro txfp tx frame data pointer tx frame pointer index to the frame data register for access. this field is reset to the next available tx frame location when the tx frame data has been enqueued through the txq command register. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 215 revision 1.0 rx frame data pointer register (0x186 C 0x187): rxfdpr bits [10:0] of this register determine the address to be accessed within the rxq fr ame buffer. when the auto increment function is set, it will automatically increment the rxq pointer on read accesses to the data register. the counter is incremented is by one for every byte access, by two for every word access, and by four f or every double word access. bit default value r/w description 15 ? ro reserved 14 0 rw rxfpai rx frame pointer auto increment 1 = when this bit is set, the rxq address register increments automatically on accesses to the data register. the increment is by one for every byte access, by two for every word access, and by four for every double word access. 0 = when this bit is reset, the rx frame data pointer is manually controlle d by user to access the rx frame location. 13 ? ro reserved 12 1 rw wst write sample time this bit is used to select the wrn active to write data valid time as shown in figure 22 . 0 = wrn active to write data valid sample time is range of 8 ns (min imum ) to 16ns (max imum ). 1 = wrn active to write data valid sample time is 4ns (max imum ). 11 ? rw ems endian mode selection this bit indicates the mode of the 8/16 - bit host interface C either big endian or little endian. the mode is determined at reset or power up by the strap - in function on pin 62, and should not be changed when writing to this register . 0 = set to little endian mode 1 = set to big endian mode 10?0 0x000 wo rxfp rx frame pointer rx frame data pointer index to the data register for access. this pointer value must reset to 0x000 before each dma operation from the host cpu to read rxq frame buffer. 0x188 C 0x18b: reserved rx duration timer threshold register (0x18c C 0x18d): rxdttr this register is used to program the received frame duration timer threshold. bit default value r/w description 15?0 0x0000 rw rxdtt receive duration timer threshold these bits are used to program the received frame duration timer threshold value in 1s increments. the maximum value is 0xcfff. when bit [7] is set to 1 in rxqcr register, the ksz8462 will set the rx interrupt ( bit [13] in isr) after the timer starts at the first received frame in the rxq buffer and when it exceeds the threshold set in this register. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 216 revision 1.0 rx data byte count threshold register (0x18e C 0x18f): rxdbctr this register is used to program the received data byte count threshold. bit default value r/w description 15?0 0x0000 rw rxdbct receive data byte count threshold these bits are used to program the received data byte threshold value in byte count. when bit [6] is set to 1 in rxqcr register, the ksz8462 will set the rx interrupt ( bit [13] in isr) when the number of received bytes in the rxq buffer exceeds the threshold set in this register. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 217 revision 1.0 internal i/o register space mapping for interrupt registers (0x190 C 0x193) interrupt enable register (0x190 C 0x191): ier this register enables the interrupts from the qmu, ptp and other sources. bit default value r/w description 15 0 rw lcie link change interrupt enable 1 = when this bit is set, the link change interrupt is enabled. 0 = when this bit is reset, the link change interrupt is disabled. 14 0 rw txie transmit interrupt enable 1 = when this bit is set, the transmit interrupt is enabled. 0 = when this bit is reset, the transmit interrupt is disabled. 13 0 rw rxie receive interrupt enable 1 = when this bit is set, the receive interrupt is enabled. 0 = when this bit is reset, the receive interrupt is disabled. 12 0 ro ptp timestamp interrupt enable t his status bit is an or of the ptp_ts_ie[ 11:0] bits. clearing the appropriate enable bit in the ptp_ts_ie register ( 0x68e C 0x68f) or clearing the appropriate status bit in the ptp_ts_is register (0x68c C 0x68d) will clear this bit. when writing this register, always write this bit as a zero. 11 0 rw rxoie receive overrun interrupt enable 1 = when this bit is set, the receive overrun interrupt is enabled. 0 = when this bit is reset, the receive overrun interrupt is disabled. 10 0 ro ptp trigger output unit interrupt enable t his status bit is an or of the ptp_trig_ie[11:0] bits. clearing the appropriate enable bit in the ptp_trig_ie register ( 0x68a C 0x68b) or clearing the appropriate status bit in the ptp_trig_is register (0x688 C 0x689) will clear this bit. when writing this register, always write this bit as a zero. 9 0 rw txpsie transmit process stopped interrupt enable 1 = when this bit is set, the transmit process stopped interrupt is enabled. 0 = when this bit is reset, the transmit process stopped interrupt is disabled. 8 0 rw rxpsie receive process stopped interrupt enable 1 = when this bit is set, the receive process stopped interrupt is enabled. 0 = when this bit is reset, the receive process stopped interrupt is disabled. 7 0 rw reserved 6 0 rw txsaie transmit space available int errupt enable 1 = when this bit is set, the transmit memory space available interrupt is e nabled. 0 = when this bit is reset, the transmit memory space available interrupt is disabled. 5 0 rw rxwfdie receive wake?up frame detect interrupt enable 1 = when this bit is set, the receive wake - up frame detect interrupt is enabled. 0 = when this bit is reset, the receive wake - up frame detect interrupt is disabled. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 218 revision 1.0 interrupt enable register (0x190 C 0x191): ier (continued) bit default value r/w description 4 0 rw rxmpdie receive magic packet detect interrupt enable 1 = when this bit is set, the receive magic packet detect interrupt is enabled. 0 = when this bit is reset, the receive magic packet detect interrupt is disabled. 3 0 rw ldie linkup detect interrupt enable 1 = when this bit is set, the wake?up from link - up detected interrupt is enabled. 0 = when this bit is reset, the wake?up from link - up detected interrupt is disabled. 2 0 rw edie energy detect interrupt enable 1 = when this bit is set, the wake?up from energy detect interrupt is enabled. 0 = when this bit is reset, the energy detect interrupt is disabled. 1C0 00 ro reserved interrupt status register (0x192 C 0x193): isr this register contains the status bits for all interrupt so urces. when the corresponding enable bit is set, it causes the interrupt pin to be asserted. this register is usually read by the host cpu and device drivers during an interrupt servi ce routine or polling. the register bits are not cleared when read. the user has to write a 1 to clear. bit default value r/w description 15 0 ro (w1c) lcis link change interrupt status when this bit is set, it indicates that the link status has changed from link up t o link down, or link down to link up. this edge?triggered interrupt status is cleared by writing a 1 to this bit. 14 0 ro (w1c) txis transmit interrupt status when this bit is set, it indicates that the txq mac has transmitted at least a frame on the mac interface and the qmu txq is ready for new frames from the host. this edge?triggered interrupt status is cleared by writing a 1 to this bit. 13 0 ro (w1c) rxis receive interrupt status when this bit is set, it indicates that the qmu rxq has received at least a frame fr om the mac interface and the frame is ready for the host cpu to process. this edge?triggered interrupt status is cleared by writing a 1 to this bit. 12 0 ro (w1c) ptp timestamp interrupt status when this bit is set, it indicates that one of 12 timestamp input units is ready (ts_rdy = 1) or the egress timestamp is available from either port 1 or port 2. this edge?triggered interrupt status is cleared by writing a 1 to this bit. 11 0 ro (w1c) rxois receive overrun interrupt status when this bit is set, it indicates that the receive overrun status has occurred. this edge?triggered interrupt status is cleared by writing a 1 to this bit. 10 0 ro (w1c) ptp trigger unit interrupt status when this bit is set, it indicates that one of 12 trigger output units is done or has an error. this edge?triggered interrupt status is cleared by writing a 1 to this bit. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 219 revision 1.0 interrupt status register (0x192 C 0x193): isr (continued) bit default value r/w description 9 0 ro (w1c) txpsis transmit process stopped interrupt status when this bit is set, it indicates that the transmit process has stopped. this edge?triggered interrupt status is cleared by writing a 1 to this bit. 8 0 ro (w1c) rxpsis receive process stopped interrupt status when this bit is set, it indicates that the receive process has st opped. this edge?triggered interrupt status is cleared by writing a 1 to this bit. 7 0 ro reserved 6 0 ro (w1c) txsais transmit space available interrupt status when this bit is set, it indicates that transmit memory space available status has occurred. 5 0 ro rxwfdis receive wake - up frame detect interrupt status when this bit is set, it indicates that a wake - up frame has been received. write 1000 to pmctrl[5:2] to clear this bit. 4 0 ro rxmpdis receive magic packet detect interrupt status when this bit is set, it indicates that a magic packet has been received. write 0100 to pmctrl[5:2] to clear this bit. 3 0 ro ldis linkup detect interrupt status when this bit is set, it indicates that wake?u p from linkup detect status has occurred. write 0010 to pmctrl[5:2] to clear this bit. 2 0 ro edis energy detect interrupt status when this bit is set and bit [2] = 1, bit [0] = 0 in the ier register, it i ndicates that wake?up from energy detect status has occurred. when this bit is set and bit [2, 0] = 1 in the ier register, it indicates that wake?up from energy detect status has occurr ed. write 0001 to pmctrl[5:2] to clear this bit. 1?0 00 ro reserved 0x194 C 0x19b : reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 220 revision 1.0 internal i/o register space mapping for the queue management unit (qmu) (0x19c C 0x1b9) rx frame count and threshold register (0x19c C 0x19d): rxfctr this register is used to program the received frame count threshold. bit default value r/w description 15?8 0x00 rw reserved 7?0 0x00 rw rxfct receive frame count threshold this register is used to program the received frame count threshold value. when bit [5] set to 1 in the rxqcr register, the device will set interrupt bit [13] in the isr when the number of received frames in rxq buffer exceeds the threshold set in this register. the count has to be at least equal to or greater than 1 to enable correct functioning of the hardware. a write of 1 to this register while the receive is enabled will result in erratic hardware operation. tx next total frames size register (0x19e C 0x19f): txntfsr this register is used by the host cpu to program the total amount of txq buffer space requested for th e next transmit. bit default value r/w description 15?0 0x0000 rw txntfsr tx next txq buffer frame space required the host cpu programs the contents of this register to indicate the total amount of txq buff er space which is required for the next one - frame transmission. it contains the frame size in double?word count ( multiples of four bytes). when bit [1] (txq memory available monitor) is set to 1 in the txqcr register, t he device will generate interrupt (bit [6] in the isr register) to the cpu when txq memory is available based u pon the total amount of txq space requested by the cpu in this register. mac address hash table register 0 (0x1a0 C 0x1a1): mahtr0 the 64?bit mac address table is used for group address filtering and it is enabled by selecting item 5 hash perfect mode in table 2 . this value is defined as the six most significant bits from crc ci rcuit calculation result that is based on 48?bit of da input. the two most significant bits select one of the four regi sters to be used, while the others determine which bit within the register. multicast table register 0 bit default value r/w description 15?0 0x0 000 rw ht0 hash table 0 when the appropriate bit is set, if the packet received with da matches the crc, the hashing function is received without being filtered. when the appropriate bit is cleared, the packet will be dropped. note : when receive all (rxcr1, bi t[4]) and the receive multicast addr. filtering with the mac address (rxcr1, bit[8]) bit is set, all multicast addresses are received r egardless of the multicast table value. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 221 revision 1.0 mac address hash table register 1 (0x1a2 C 0x1a3): mahtr1 multicast table re gister 1 bit default value r/w description 15?0 0x0 000 rw ht1 hash table 1 when the appropriate bit is set, if the packet received with da matches the crc, the ha shing function is received without being filtered. when the appropriate bit is cleared, the packet will be dropped. note : when receive all (rxcr1, bit[4]) and the receive multicast addr. filtering with th e mac address (rxcr1, bit[8]) bit is set, all multicast addresses are received r egardless of the multicast table value. mac address hash table register 2 (0x1a4 C 0x1a5): mahtr2 multicast table register 2 bit default value r/w description 15?0 0x0 000 rw ht2 hash table 2 when the appropriate bit is set, if the packet received with da matches the crc, the ha shing function is received without being filtered. when the appropriate bit is cleared, the packet will be dropped. note : when receive all (rxcr1, bit[4]) and the receive multicast addr. filtering with th e mac address (rxcr1, bit[8]) bit is set, all multicast addresses are received r egardless of the multicast table value. mac address hash table register 3 (0x1a6 C 0x1a7): mahtr3 multicast table register 3 bit default value r/w description 15?0 0x0 000 rw ht3 hash table 2 when the appropriate bit is set, if the packet received with da matches the crc, the ha shing function is received without being filtered. when the appropriate bit is cleared, the packet will be dropped. note : when receive all (rxcr1, bit[4]) and the receive multicast addr. filtering with th e mac address (rx cr1, bit[8]) bit is set, all multicast addresses are received regardless of the multicast table value. 0x1a8 C 0x1af: reserved flow control low water mark register (0x1b0 C 0x1b1): fclwr this register is used to control the flow control for low water ma rk in qmu rx queue. bit default value r/w description 15?12 ? rw reserved 11?0 0x600 rw fclwc flow control low water mark configuration these bits define the qmu rx queue low water mark configuration. it is in double words count and default is 6kb available buffer space out of 12kb. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 222 revision 1.0 flow control high water mark register (0x1b2 C 0x1b3): fchwr this register is used to control the flow control for high water mark in qmu rx queue. bit default value r/w description 15?12 ? rw reserved 11?0 0x400 rw fchwc flow control high water mark configuration these bits define the qmu rx queue high water mark configuration. it is in double words count and default is 4kb available buffer space out of 12kb. flow control overrun water mark register (0x1b4 C 0x1b5): fcowr this register is used to control the flow control for overrun water mark in qmu rx queue. bit default value r/w description 15?12 ? rw reserved 11?0 0x040 rw fclwc flow control overrun water mark configuration these bits define the qmu rx queue overrun water mark configuration. it is in double words count and default is 256 bytes available buffer space out of 12kb. rx frame count register (0x1b8 C 0x1b9): rxfc this register indicates the current total amount of received frame count in rxq frame buffer bit defau lt value r/w description 15?8 0x00 ro rxfc rx frame count i ndicate s the total received frames in rxq frame buffer when the receive interrupt (bit [13] = 1 in the isr) occurred and a '1' is written to clear this bit [13] in the isr. the host cpu can start to read the updated receive frame header information in rxfhsr/rxfhbcr registers after reading the rx frame count register 7?0 0x00 rw reserved 0x1ba C 0x1ff: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 223 revision 1.0 internal i/o register space mapping for trigger output units (12 units, 0x200 C 0x3ff) trigger error register (0x200 C 0x201): trig_err this register contains the trigger output unit error status. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 ro trigger output unit error 1 = the trigger time is set earlier than the system time clock when trig_notify bit is set to 1 in trig_cfg1 register and it will generate interrupt to host if interrupt enable bit is set in ptp_trig_ie register. this bit can be cleared by resetting the trig_en bit to 0. 0 = no trigger output unit error. there are 12 trigger output units and therefore there is a corresponding error bit for each of the tri gger output units, bit[11:0] = unit [12:1]. trigger active register (0x202 C 0x203): trig_active this register contains the trigger output unit active status. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 ro trigger output unit active 1 = the trigger output unit is enabled and active without error. 0 = the trigger output unit is finished and inactive. there are 12 trigger output units and therefore there is a corresponding active bit for each of the trigger output units , bit [11:0] = unit [12:1]. trigger done register (0x204 C 0x205): trig_done this register contains the trigger output unit event done status. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 ro (w1c) trigger output unit event done 1 = the trigger output unit event has been generated when trig_notify bit is set to 1 in trig_cfg1 register (write 1 to clear this bit) and it will generate interrupt to host if interrupt enable bit is set in ptp_trig_ie register. 0 = the trigger output unit event is not generated. there are 12 trigger output units and therefore there is a corresponding done bit for each of the trigger output units, bit [11:0] = unit [12:1]. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 224 revision 1.0 trigger enable register (0x206 C 0x207): trig_en this register contains the trigger output unit enable control bits. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 rw trigger output unit enable 1 = enables the selected trigger output unit and will self?clear when the trigger output is generated. in cascade mode, only enable the head of trigger unit. 0 = the trigger output unit is disabled. there are 12 trigger output units and therefore there is a corresponding enable bit for each of the trigger output units, bit [11:0] = unit [12:1]. trigger software reset register (0x208 C 0x209): trig_sw_rst this register contains the software reset bits for the trigger output units. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 rw /sc trigger output unit software reset 1 = when set, the selected trigger output unit is put into the inactive state and default setting. this can be used to stop the cascade mode in continuous operation and prepare the selected trigger unit for the next operation. 0 = wh ile zero, the selected trigger output unit is in normal operating mode. there are 12 trigger output units and therefore there is a corresponding software reset bit for eac h of the trigger output units, bit [11:0] = unit [12:1]. trigger output unit 12 output pps pulse width register (0x20a C 0x20b): trig12_pps_width this register contains the trigger output unit 12 pps pulse width and trigger output unit 1 path delay compensation. bit default r/w description 15?12 0x0 ro reserved 11 0 rw reserved 10?8 000 rw path delay compensation for trigger output unit 1 these three bits are used to compensate the path delay of clock skew for event trigger output unit 1 in the range of 0 ~ 7ns (bit [11] = 1) or 0 ~ 28ns (bit [11] = 0). 7?0 0x00 rw pps pulse width for trigger output unit 12 this is upper third byte [23:16] in conjunction with the unit 12 trigger output pulse width in trig12_cfg_2[15:0] (0x38a) register to make this register value for pps pulse width up to 134ms . 0x20c C 0x21f: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 225 revision 1.0 tr igger output unit 1 target time in nanosecond s low ? w ord register (0x220 C 0x221): trig1_tgt_nsl this register contains the trigger output unit 1 target time in nanoseconds low ?word. bit default r/w description 15?0 0x0000 rw trigger output unit 1 target time in nanoseconds low? word [15:0] this is low?word of target time for trigger output unit 1 in nanoseconds. trigger output unit 1 target time in nanosecond s high ? w ord register (0x222 C 0x223): trig1_tgt_nsh this register contains the trigger output unit 1 target time in nanoseconds high?word. bit default r/w description 15?14 0x0 ro reserved 13?0 0x0000 rw trigger output unit 1 target time in nanoseconds hi gh? word [29:16] this is high?word of target time for trigger output unit 1 in nanoseconds. trigger output unit 1 target time in second s low ? w ord register (0x224 C 0x225): trig1_tgt_sl this register contains the trigger output unit 1 target time in seconds low?wor d. bit default r/w description 15?0 0x0000 rw trigger output unit 1 target time in seconds low? word [15:0] this is low?word of target time for trigger output unit 1 in seconds. trigger output unit 1 target time in second s high ? w ord register (0x226 C 0x227): trig1_tgt_sh this register contains the trigger output unit 1 target time in seconds high?word. bit default r/w description 15?0 0x0000 rw trigger output unit 1 target time in seconds high? word [31:16] this is high?word of target time for trigger output unit 1 in seconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 226 revision 1.0 trigger output unit 1 configuration and control register 1 (0x228 C 0x229): trig1_cfg_1 this register (1 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15 0 rw enable this trigger output unit in cascade mode 1 = enable this trigger output unit in cascade mode. 0 = disable this trigger output unit in cascade mode. 14 0 rw indicate a tail unit for this trigger output unit in cascad e mode 1 = this trigger output unit is the last unit of the chain in cascade mode. 0 = this trigger output unit is not the last unit of a chain in cascade mode. note: when this bit is set 0 in all cfg_1 trigger units, and all units are in cascade mode, the iteration count is ignored and it becomes infinite. to stop the i nfinite loop, set the respective bit[11:0] in trig_sw_rst register. 13 ? 10 0xf rw select upstream trigger unit in cascade mode these bits select one of the 12 upstream trigger output unit s in cascade mode. note that 0x0 indicates tou1, and 0xb indicates tou12. (values 0xc to 0xf do not indicate any tou.) for example, if units 1, 2 and 3 (tail unit) are set up in cascade mode, then these 4 bits are set as follow s at the three trigger output u nits: unit 1 is s et to 0x2 (indicates tou3), at unit 2 is set to 0x0 (indicates tou1) and at unit 3 is to set 0x1 (indicates tou2) . 9 0 rw trigger now 1 = immediately create the trigger output if the trigger target time is less than the system time clock. 0 = wait for the trigger target time to occur to trigger the event output. 8 0 rw trigger notify 1 = e nable reporting both trig_done and trig_err status as well as interrupt to host if the interrupt enable bit is set in the trig_ie register. 0 = d isable reporting both trig_done and trig_err status. 7 0 ro reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 227 revision 1.0 trigger output unit 1 configuration and control register 1 (0x228 C 0x229): trig1_cfg_1 (continued) bit default r/w description 6 ? 4 000 rw trigger output signal pattern this field select s the trigger output signal pattern when trig_en = 1 and trigger target time has reached the system time: 000: trig_neg_edge ? generates negative edge (from default h ?> l an d stays l). 001: trig_pos_edge ? generates positive edge (from defa ult l ?> h and stays h). 010: trig_neg_pulse ? generates negative pulse (from default h ?> l pulse ?> h and stays h). the pulse width is defined in trig1_cfg_2 register. 011: trig_pos_pulse ? generates positive pulse (from defau lt l ?> h pulse ? > l and stays l). the pulse width is defined in trig1_cfg_2 register. 100: trig_neg_cycle ? generates negative periodic signal. the l pulse w idth is defined in trig1_cfg_2 register, the cycle width is defined in trig1_cfg_3/4 registers and the number of cycles is defined in trig1_cfg_5 register (it is an infinite number if this register value is zero). 101: trig_pos_cycle ? generates positive periodic signal. the h puls e width is defined in trig1_cfg_2 register, the cycle width is defined in trig1_cfg_3/4 registers and the number of cycles is defined in trig1_cfg_5 register (it is an infinite number if this register value is zero). 110: trig_reg_output ? generates an output signal from a 16?bit regist er. this 16?bit register bit?pattern in trig1_cfg_6 is shifted lsb bit fi rst and looped, each bit width is defined in trig1_cfg_3/4 registers and total number of bits to shift out is defined in trig1_c fg_5 register (it is an infinite number if this register value is zero). 111: reserved note : the maximum output clock frequency is up to 12.5mhz. 3 ? 0 0x0 rw select gpio[6:0] for this trigger output unit a ssociate s one of the 7 gpio pins to this trigger output unit. the trigger output signals are ored together to form a combined signal if multiple trigger output units have selected the sam e gpio output pin. 0x0 indicates gpio0 , and 0x 6 indicates gpio6 . ( 0x7 to 0xf are not used. ) downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 228 revision 1.0 trigger output unit 1 configuration and control register 2 (0x22a C 0x22b): trig1_cfg_2 this register (2 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15?0 0x0000 rw trigger output pulse width this number defines the width of the generated pulse or periodic signal from this trigger output unit. its unit value is equal to 8ns. for example, the pulse width is 80ns if this register value is 10 ( 0xa). iteration count this number defines the iteration count for register trigger output pattern (trig1_cfg_6) in cascade mode when this trigger output unit is the tail unit. for example, 0x0000 = 1 count and 0x000f = 16 counts. it is an infinite number if there is no tail unit in cascade mode. trigger output unit 1 configuration and control register 3 (0x22c C 0x22d): trig1_cfg_3 this register (3 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15?0 0x0000 rw trigger output cycle width or bit width low? word [15:0] to define cycle width for generating periodic signal or to define each bit width in trig1_cfg _8. a unit number of value equals to 1ns. for example, the cycle or bit width is 80ns if this register v alue is 80 (0x50) and next register value = 0x0000. trigger output unit 1 configuration and control register 4 (0x22e C 0x22f): trig1_cfg_4 this register (4 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15?0 0x0000 rw trigger output cycle width bit o r width high? word [31:16] this number defines the cycle width when generating periodic signals using this trigger output un it. also, it is used to define each bit width in trig1_cfg_8. each unit is equal to 1ns. trigger output unit 1 configuration and control register 5 (0x230 C 0x231): trig1_cfg_5 this register (5 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15?0 0x0000 rw trigger output cycle count this number defines the quantity of cycles of the periodic signal output by the trigger output unit. use a value of zero for infinite repetition. valid for trig_neg_cycle and trig_pos_cycl e modes. bit count this number can define the number of bits that ar e output when generating output signals from the bit pattern register. it is an infinite number if this register value is zero. valid for trig_reg _output mode. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 229 revision 1.0 trigger output unit 1 configuration and control register 6 (0x232 C 0x233): trig1_cfg_6 this register (6 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15?0 0x0000 rw trigger output unit bit pattern t his register is used to define the output bit pattern when the trig_reg_output mode is selected . iteration count this register is used as the iteration count for the trigger output unit when the tail unit is in cascade mode but not using register mode. it is the number of cycles programmed in cfg_5 to be ou tput by the trigger output unit. for example, 0x0000 =1 count, 0x000f =16 counts. an infinite number of cycles will occur if there is no tail unit in cascade mode. trigger output unit 1 configuration and control register 7 (0x234 C 0x235): trig1_cfg_7 this register (7 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15?0 0x0000 rw trigger output iteration cycle time in cascade mode low? word [15:0] the value in this pair of registers defines the iteration cycle time for the trigger o utput unit in cascade mode. this value will be added to the current trigger target time for establishing the next trigger time for the trigger output unit. a unit number of value equals to 1ns. for example, the cycle is 800 ns if t his register value is 800 (0x320) and next register value = 0x0000. the iteration count (cfg_6) x trigger output cycle count (cfg_5) x waveform cycle time must be less than the iteration cycle t ime specified in cfg_7 and cfg_8. trigger output unit 1 configuration and control register 8 (0x236 C 0x237): trig1_cfg_8 this register (8 of 8) contains the trigger output unit 1 configuration and control bits. bit default r/w description 15?0 0x0000 rw trigger output iteration cycle time in cascade mode high? word [31:16] the value in this pair of registers defines the iteration cycle time for the trigger o utput unit in cascade mode. this value will be added to the current trigger target time for establishing the next trigger time for the trigger output unit. a unit number of value equals 1ns. 0x238 C 0x23f: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 230 revision 1.0 trigger output unit 2 target time and output configuration/control registers (0x24 0 C 0x2 5 7) these 12 registers contain the trigger output unit 2 target time and configuration/control bits, trig2_cf g_[1:8]. see descriptions in the trigger output unit 1 registers (0x220 C 0x237). note that there is one bit that is different in this set of regist er bits. it is indicated below. trigger output unit 2 configurat ion and control register 1 (0x248 C 0x249): trig2 _cfg_1 this register contains the trigger output unit 2 configuration and control bits. bit default r/w description 7 0 rw trigger unit 2 clock edge output select this bit is used to select either the positive edge or negative edge of the 125mhz to clock out the tr igger unit 2 output. this bit only pertains to usage with gpio1 pin. this bit will not function with any other gpio pin. 1 = use negative edge of 125mhz clock to clock out data 0 = use positive edge of 125mhz clock to clock out data 0x258 C 0x25f: reserved trigger output unit 3 target time and output configuration/control registers (0x26 0 C 0x277) these 12 registers contain the trigger output unit 3 target time and configuration/control bits, trig3_cf g_[1:8]. see descriptions in the trigger output unit 1 registers (0x220 C 0x237). 0x278 C 0x27f: reserved trigger output unit 4 target time and output configuration/control registers (0x28 0 C 0x297) these 12 registers contain the trigger output unit 4 target time and configuration/control bits, trig4_cf g_[1:8]. see descriptions in the trigger output unit 1 registers (0x220 C 0x237). 0x298 C 0x29f: reserved trigger output unit 5 target time and output configuration/control registers (0x2a 0 C 0x2b7) these 12 registers contain the t rigger o utput unit 5 target time and configuration/control bits, trig5 _cfg_[1:8]. see descriptions in the t rigger o utput u nit 1 r egisters (0x220 C 0x237). 0x2b8 C 0x2bf: reserved trigger output unit 6 target time and output configuration/control registers (0x2c 0 C 0x2d7) these 12 registers contain the t rigger o utput unit 6 target time and configuration/control bits, trig6 _cfg_[1:8]. see descriptions in the t rigger o utput u nit 1 r eg isters (0x220 C 0x237). 0x2d8 C 0x2df: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 231 revision 1.0 trigger output unit 7 target time and output configuration/control registers (0x2e 0 C 0x2f7) these 12 registers contain the t rigger o utput unit 7 target time and configuration/control bits, trig7 _cfg_[ 1:8]. see descriptions in the t rigger o utput u nit 1 r egisters (0x220 C 0x237). 0x2f8 C 0x2ff: reserved trigger output unit 8 target time and output configuration/control registers (0x30 0 C 0x317) these 12 registers contain the t rigger o utput unit 8 targe t time and configuration/control bits, trig8 _cfg_[1:8]. see descriptions in the t rigger o utput u nit 1 r egisters (0x220 C 0x237). 0x318 C 0x31f: reserved trigger output unit 9 target time and output configuration/control registers (0x32 0 C 0x337) these 12 registers contain the t rigger o utput unit 9 target time and configuration/control bits, trig9 _cfg_[1:8]. see descriptions in the t rigger o utput u nit 1 r egisters (0x220 C 0x237). 0x338 C 0x33f: reserved trigger output unit 10 target time and output configuration/control registers (0x34 0 C 0x357) these 12 registers contain the t rigger o utput unit 10 target time and configuration/control bits, trig10 _cfg_[1:8]. see descriptions in the t rigger o utput u nit 1 r egisters (0x220 C 0x237). 0x358 C 0x35f: reserved trigger output unit 11 target time and output configuration/control registers (0x36 0 C 0x377) these 12 registers contain the t rigger o utput unit 11 target time and configuration/control bits, trig11 _cfg_[1:8]. see descriptions in the t rigger o utput u nit 1 r egisters (0x220 C 0x237). 0x378 C 0x37f: reserved trigger output unit 12 target time and output configuration/control registers (0x38 0 C 0x397) these 12 registers contain the t rigger o utput unit 12 target time and configuration/control bits , trig12 _cfg_[1:8]. see descriptions in the t rigger o utput u nit 1 r egisters (0x220 C 0x237). 0x398 C 0x3ff: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 232 revision 1.0 internal i/o register space mapping for ptp timestamp inputs (12 units, 0x400 C 0x5ff) timestamp ready register (0x400 C 0x401): ts_rdy this register contains the ptp timestamp input unit ready to read status bits. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 ro timestamp input unit ready 1 = this timestamp input unit is ready to read and will generate a timestamp interrupt if ptp_ts_ie = 1. this bit will clear when ts_en is disabled. 0 = this timestamp input unit is not ready to read or disabled. there are 12 timestamp units and therefore there is a corresponding timestamp input ready bi t for each of the timestamp units, bit[11:0] = unit [12:1]. timestamp enable register (0x402 C 0x403): ts_en this register contains the ptp timestamp input unit enable control bits. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 rw timestamp input unit enable 1 = enable the selected timestamp input unit. writing a 1 to this bit will clear the ts[12:1]_event_det_cnt. 0 = disable the selected timestamp input unit. writing a 0 to this bit will clear the ts_rdy and ts[12:1]_det_cnt_ovfl. there are 12 timestamp units and therefore there is a corresponding timestamp input unit e nable bit for each of the timestamp unit s, bit[11:0] = unit [12:1]. timestamp software reset register (0x404 C 0x405): ts_sw_rst this register contains the ptp timestamp input unit software reset control bits. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 rw /sc timestamp input unit software reset 1 = reset the selected timestamp input unit to inactive state and default setting. 0 = the selected timestamp input unit is in normal mode of operation. there are 12 timestamp units and therefore there is a corresponding timestamp inpu t unit software reset bit for each of the timestamp units , bit [11:0] = unit [12:1]. 0x406 C 0x41f: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 233 revision 1.0 timestamp unit 1 status register (0x420 C 0x421): ts1_status this register contains ptp timestamp input unit 1 status. bit default r/w description 15?5 0x000 ro reserved 4?1 0x0 ro number of detected event count for timestamp input unit 1 (ts 1_event_det_cnt) this field is used to report the number of detected events (either rising or falling edge) coun t. in single mode, it can detect up to 15 events in any single timestamp input unit. in cascade mode, it can detect up to two events in timestamp input units 1?1 1 or up to 8 events at timestamp input unit 12 as a non?tail unit, and it can detect up to 15 events for any timestamp input unit as a tail unit. pulses or edges can be detected up to 25mhz. the pulse width can be measured by the difference between consecu tive timestamps in the same timestamp input unit. 0 0 ro number of detected event count overflow for timestamp input unit 1 (ts1_det_cnt_ovfl) 1 = the number of detected event (either rising or falling edge) count has overflowed . in cascade mode, only tail unit will set this bit when overflow has occurred. the ts1_event_det_cnt will stay at 15 when overflow has occurred. 0 = the number of events (either rising or falling edge) detected count has not overflowed. timestamp u nit 1 configuration and control register (0x422 C 0x423): ts1_cfg this register contains ptp timestamp input unit 1 configuration and control bits. bit default r/w description 15?12 0x0 ro reserved 11 ? 8 0x0 rw select gpio[6:0] for timestamp unit 1 this field is used to select one of the 7 gpio pins to serve this timestamp unit. it is g pio0 if these bits = 0000 and it is gpio6 if these bits = 0110 (from 0111 to 1111 are not used). 7 0 rw enable rising edge detection 1 = enable rising edge detection. 0 = disable rising edge detection. 6 0 rw enable falling edge detection 1 = enable falling edge detection. 0 = disable falling edge detection. 5 0 rw select tail unit for this timestamp unit in cascade mode 1 = this timestamp unit is the last unit of the chain in cascade mode. 0 = this timestamp unit is not the last unit of the chain in cascade mode. 4 ? 1 0x0 rw select upstream timestamp done unit in cascade mode this is used to select one of the 12 upstream timestamps units for done input in cas cade mode. for example, if units 1 (head unit), 2 and 3 (tail unit) are set up in cascade mode , then these 4?bits at unit 1 are set to 0x0, at unit 2 are set to 0x1, at unit 3 are set to 0x2. 0 0 rw enable this timestamp unit in cascade mode 1 = enable the selected timestamp input unit in cascade mode. 0 = disable the timestamp input unit in cascade mode. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 234 revision 1.0 timestamp unit 1 input 1st sample time in nanosecond s low ? word register (0x424 C 0x425): ts1_smpl1_nsl this register contains the first sample time in nanoseconds low?word (the resolution of 40ns) for ptp timestamp unit 1. bit default r/w description 15?0 0x0000 ro 1 st sample time in ns low? word [15:0] timestamp unit 1 this is the low?word of first sample time for timestamp unit 1 i n nanoseconds. timestamp unit 1 input 1st sample time in nanosecond s high ? word register (0x426 C 0x427): ts1_smpl1_nsh this register contains the first sample time in nanoseconds high?word and edge detect ion status for ptp timestamp unit 1. bit default r/w description 15 0 ro reserved 14 0 ro 1 st sample edge indication for timestamp unit 1 0 = indicates the event is a falling edge signal. 1 = indicates the event is a rising edge signal. 13?0 0x0000 ro 1 st sample time in ns high?word [29:16] for timestamp unit 1 this is the high?word of first sample time for timestamp unit 1 in nanos econds. timestamp unit 1 input 1st sample time in second s low ? word register (0x428 C 0x429): ts1_smpl1_sl this register contains the first sample time in seconds low?word for p tp tim estamp unit 1. bit default r/w description 15?0 0x0000 ro 1 st sample time in seconds low? word [15:0] for timestamp unit 1 this is the low?word of first sample time for timestamp unit 1 in sec onds. timestamp unit 1 input 1st sample time in second s high ? word register (0x42a C 0x42b): ts1_smpl1_sh this register contains the first sample time in seconds high?word for ptp timestamp unit 1. bit default r/w description 15?0 0x0000 ro 1 st sample time in seconds high? word [31:16] for timestamp unit 1 this is the high?word of first sample time for timestamp unit 1 in seconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 235 revision 1.0 timestamp unit 1 input 1st sample time in sub?nanosecon ds register (0x42c C 0x42d): ts1_smpl1_sub_ns this register contains the first sample time in sub - 8 nanoseconds (the resolution of 8ns) for ptp timestamp unit 1. bit default r/w description 15?3 0x0000 ro reserved 2?0 000 ro 1 st sample time in sub 8ns for timestamp unit 1 these bits indicate one of the 8ns cycle s for the first sample time for timestamp unit 1. 000: 0ns (sample time at the first 8ns cycle in 25mhz/40ns) 001: 8ns (sample time at the second 8ns cycle in 25mhz/40ns) 010: 16ns (sample time at the third 8ns cycle in 25mhz/40ns) 011: 24ns (sample time at the fourth 8ns cycle in 25mhz/40ns) 100: 32ns (sample time at the fifth 8 ns cycle in 25mhz/40ns) 101?111: na 0x42e C 0x433: reserved timestamp unit 1 input 2nd sample time in nanosecond s low ? word register (0x434 C 0x435): ts1_smpl2_nsl this register contains the 2nd sample time in nanoseconds low?word (the resolution of 40ns) for p tp timestamp unit 1. bit default r/w description 15?0 0x0000 ro 2 nd sample time in ns. for low?word [15:0] for timestamp unit 1 this is the low?word of the 2nd sample time for timestamp unit 1 in nanoseconds. timestamp unit 1 input 2nd sample time in nanosecond s high ? word register (0x436 C 0x437): ts1_smpl2_nsh this register contains the 2nd sample time in nanoseconds low ?word and edge detection status for the ptp timestamp unit 1. bit default r/w description 15 0 ro reserved 14 0 ro 2nd sample edge indication for timestamp unit 1 0 = indicates the event is a falling edge signal. 1 = indicates the event is a rising edge signal. 13?0 0x0000 ro 2nd sample time in ns. high? word [29:16] for timestamp unit 1 this is the high?word of the 2nd sample time for timestamp unit 1 in nanose conds. timestamp unit 1 input 2nd sample time in second s low ? word register (0x438 C 0x439): ts1_smpl2_sl this register contains the 2nd sample time in seconds low?word for ptp ti mestamp unit 1. bit default r/w description 15?0 0x0000 ro 2nd sample time in seconds low? word [15:0] for timestamp unit 1 this is the low?word of the 2nd sample time for timestamp unit 1 in seconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 236 revision 1.0 timestamp unit 1 input 2nd sample time in second s high ? word register (0x43a C 0x43b): ts1_smpl2_sh this register contains the 2nd sample time in seconds high?word for ptp times tamp unit 1. bit default r/w description 15?0 0x0000 ro 2nd sample time in seconds high? word [31:16] for timestamp unit 1 this is the high?word of the 2nd sample time for timestamp unit 1 in s econds. timestamp unit 1 input 2nd sample time in sub ? nanosecond s register (0x43c C 0x43d): ts1_smpl2_sub_ns this register contains the 2nd sample time in sub 8 nanoseconds (the resolution of 8ns) for ptp ti mestamp unit 1. bit default r/w description 15?3 0x0000 ro reserved 2?0 000 ro 2nd sample time in sub 8ns for timestamp unit 1 these bits indicate one of the 8ns cycle s for the second sample time for timestamp unit 1. 000: 0ns (sample time at the first 8ns cycle in 25mhz/40ns) 001: 8ns (sample time at the second 8ns cycle in 25mhz/40ns) 010: 16ns (sample time at the third 8ns cycle in 25mhz/40ns) 011: 24ns (sample time at the fourth 8ns cycle in 25mhz/40ns) 100: 32ns (sample time at the fifth 8ns cycle in 25mhz/40ns) 101?111: na 0x43e C 0x43f: reserved timestamp unit 2 status/configuration/control and input 1st sample time registers (0x440 C 0x44d) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp uni t 2. see description in timestamp unit 1 (0x420 C 0x42d). 0x44e C 0x453: reserved timestamp unit 2 input 2nd sample time registers (0x454 C 0x45d) these 5 registers contain the 2nd sample time for ptp timestamp unit 2. se e description in timestamp unit 1 (0x434 C 0x43d). 0x45e C 0x45f: reserved timestamp unit 3 status/configuration/control and input 1st sa mple time registers (0x460 C 0x46d) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp unit 3. see description in timestamp unit 1 (0x420 C 0x42d). 0x46e C 0x473: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 237 revision 1.0 timestamp unit 3 input 2 nd sample time registers (0x474 C 0x47d) these 5 registers contain the 2nd sample time for ptp timestamp unit 3. see d escription in timestamp unit 1 (0x434 C 0x43d). 0x47e C 0x47f: reserved timestamp unit 4 status/configuration/control and input 1st sam ple time registers (0x480 C 0x48d) these 7 registers contain the1 st sample time and status/configuration/control information for ptp timestamp uni t 4. see description in timestamp unit 1 (0x420 C 0x42d). 0x48e C 0x493: reserved timestamp unit 4 input 2nd sample time registers (0x494 C 0x49d) these 5 registers contain the 2nd sample time for ptp timestamp unit 4 input. see description in timestamp unit 1 (0x434 C 0x43d). 0x49e C 0x49f: reserved timestamp unit 5 status/configuration/control and input 1st sample time registers (0x4a0 C 0x4ad) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp uni t 5. see description in timestamp unit 1 (0x420 C 0x42d). 0x4ae C 0x4b3: reserved timestamp unit 5 input 2nd sample time registers (0x4b4 C 0x4bd) these 5 registers contain the 2nd sample time for ptp timestamp unit 5. see d escription in timestamp unit 1 (0x434 C 0x43d). 0x4be C 0x4bf: reserved timestamp unit 6 status/configuration/control and input 1st sa mple time registers (0x4c0 C 0x4cd) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp uni t 6. see description in timestamp unit 1 (0x420 C 0x42d). 0 x4ce C 0x4d3: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 238 revision 1.0 timestamp unit 6 input 2nd sample time registers (0x4d4 C 0x4dd) these 5 registers contain the 2nd sample time for ptp timestamp unit 6. see d escription in timestamp unit 1 (0x434 C 0x43d). 0x4de C 0x4df: reserved timestamp unit 7 status/configuration/control and input 1st sam ple time registers (0x4e0 C 0x4ed) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp uni t 7. see description in timestamp unit 1 (0x420 C 0x42d). 0x4ee C 0x4f3: reserved timestamp unit 7 input 2nd sample time registers (0x4f4 C 0x4fd) these 5 registers contain the 2nd sample time for ptp timestamp unit 7. see d escription in timestamp unit 1 (0x434 C 0x43d). 0x4fe C 0x4ff: reserved timestamp unit 8 status/configuration/control and input 1st sam ple time registers (0x500 C 0x50d) these 7 registers contain the1 st sample time and status/configuration/control information for ptp timestamp uni t 8. see description in timestamp unit 1 (0x420 C 0x42d). 0x50e C 0x513: reserved timestamp unit 8 input 2nd sample time registers (0x514 C 0x51d) these 5 registers contain the 2nd sample time for ptp timestamp unit 8. see d escription in timestamp unit 1 (0x434 C 0x43d). 0x51e C 0x51f: reserved timestamp unit 9 status/configuration/control and input 1st sample time registers (0x520 C 0x52d) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp uni t 9. see description in timestamp unit 1 (0x420 C 0x42d). 0x52e C 0x533: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 239 revision 1.0 timestamp unit 9 input 2nd sample time registers (0x534 C 0x53d) these 5 registers contain the 2nd sample time for ptp timestamp unit 9. see description in timestamp unit 1 (0x434 C 0x43d). 0x53e C 0x53f: reserved timestamp unit 10 status/configuration/control and input 1st sampl e time registers (0x540 C 0x54d) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp unit 10. see description in timestamp unit 1 (0x420 C 0x42d). 0x54e C 0x553: reserved timestamp unit 10 input 2nd sample time registers (0x554 C 0x55d) these 5 registers contain the 2nd sample time for ptp timestamp unit 10. see description in timestamp unit 1 (0x434 C 0x43d). 0x55e C 0x55f: reserved timestamp unit 11 status/configuration/control and input 1st sample time registers (0x560 C 0x56d) these 7 registers contain the1 st sample time and status/configuration/control information for ptp timestamp uni t 11. see description in timestamp unit 1 (0x420 C 0x42d). 0x56e C 0x573: reserved timestamp unit 11 inpu t 2nd sample time registers (0x574 C 0x57d) these 5 registers contain the 2nd sample time for ptp timestamp unit 11. see description in timestamp unit 1 (0x434 C 0x43d). 0x57e C 0x57f: reserved timestamp unit 12 status/configuration/control and input 1st sample time registers (0x580 C 0x58d) ( note : timestamp unit 12 has eight sample time registers available) these 7 registers contain the 1 st sample time and status/configuration/control information for ptp timestamp unit 12. see description in timestamp unit 1 (0x420 C 0x42d). 0x58e C 0x593: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 240 revision 1.0 timestamp unit 12 input 2nd sample time registers (0x594 C 0x59d) these 5 registers contain the 2nd sample time for ptp timestamp unit 12. see description in timestamp unit 1 (0x434 C 0x43d). 0x59e C 0x5a3: reserved timestamp unit 12 input 3rd sample time registers (0x5a4 C 0x5ad) these 5 registers contain the 3rd sample time for ptp timestamp unit 12. see des cription in timestamp unit 1 (0x434 C 0x43d). 0x5ae C 0x5b3: reserved timestamp unit 12 input 4th sample time registers (0x5b4 C 0x5bd) these 5 registers contain the 4th sample time for ptp timestamp unit 12. see desc ription in timestamp unit 1 (0x434 C 0x43d). 0x5be C 0x5c3: reserved timestamp unit 12 input 5th sample time registers (0x5c4 C 0x5cd) these 5 registers contain the 5th sample time for ptp timestamp unit 12. see desc ription in timestamp unit 1 (0x434 C 0x43d). 0x5ce C 0x5d3: reserved timestamp unit 12 input 6th sample time registers (0x5d4 C 0x5dd) these 5 registers contain the 6th sample time for ptp timestamp unit 12. see desc ription in timestamp unit 1 (0x434 C 0x43d). 0x5de C 0x5e3: reserved timestamp unit 12 input 7th sample time registers (0x5e4 C 0x5ed) these 5 registers contain the 7th sample time for ptp timestamp unit 12. see desc ription in timestamp unit 1 (0x434 C 0x43d).0x5ee C 0x5f3 : reserved 0x5ee C 0x5f3: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 241 revision 1.0 timestamp unit 12 input 8th sample time registers (0x5f4 C 0x5fd) these 5 registers contain the 8th sample time for ptp timestamp unit 12. see desc ription in timestamp unit 1 (0x434 C 0x43d). 0x5fe C 0x5ff: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 242 revision 1.0 internal i/o register space mapping for ptp 1588 clock and global control (0x600 C 0x7ff) ptp clock control register (0x600 C 0x601): ptp_clk_ctl this register contains control of ptp 1588 clock. bit default r/w description 15?7 0x000 ro reserved 6 0 rw/sc (self clear) enable step adjustment mode to ptp 1588 clock (ptp_step_adj_clk) setting this bit will cause the time value in ptp_rtc_nsh/l registers to be added (ptp_step_dir, bit [5 ] = 1 or subtracted (ptp_step_dir, bit [5] = 0 ) from the system time clock. this bit is self ? clearing. 5 0 rw direction control for step adjustment mode (ptp_step_dir) 1 = to add the time value in ptp_rtc_nsh/l registers to system time clock. 0 = to subtract the time value in ptp_rtc_nsh/l registers from system time clock. 4 0 rw/sc (self clear) enable read ptp 1588 clock (ptp_read_clk) setting this bit will cause the device to sample the ptp 1588 clock time value. this time value will be made available for reading through the ptp_rtc_sh/l, ptp_rtc_nsh/l and ptp_rtc_phase registers. this bit is self ? clearing. 3 0 rw/sc (self clear) enable load ptp 1588 clock for direct time setting mode (ptp_load_clk) setting this bit will cause the device to load the ptp 1588 clock time value from ptp_r tc_sh/l, ptp_rtc_nsh/l and ptp_rtc_phase registers. the writes to ptp_rtc_sh/l, ptp_rtc_nsh/l and ptp_rtc_phase are performed before setting this bit. this bit is self ? clearing. 2 0 rw enable continuous adjustment mode for ptp 1588 clock (ptp_continu_adj_clk ) 1 = e nable continuous incrementing (ptp_rate_dir = 0) or decrementing (ptp_rate_dir = 1) frequency adjustment by the value in ptp_sns_rate_h [29:16] and ptp_sns_rate_l [15:0] on ev ery 25mhz clock cycle. 0 = disable continuous adjustment mode to ptp 1588 clock. 1 1 rw enable ptp 1588 clock (en_ptp_clk) 1 = e nable the ptp clock. 0 = d isable the ptp clock and the ptp clock will be frozen. for non? ptp mode, this bit is set to 0 for stopping clock toggling. 0 0 rw/sc (self clear) reset ptp 1588 clock (reset_ptp_clk) setting this bit will reset the ptp 1588 clock. 0x602 C 0x603: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 243 revision 1.0 ptp real time clock in nanosecond s low ? w ord register (0x604 C 0x605): ptp_rtc_nsl this register contains the ptp real time clock in nanoseconds low?word. bit default r/w description 15?0 0x0000 rw ptp real time clock in nanoseconds low?w ord [15:0] this is low?word of the ptp real time clock in nanoseconds. ptp real time clock in nanosecond s high ? w ord register (0x606 C 0x607): ptp_rtc_nsh this register contains the ptp real time clock in nanoseconds high?word. bit default r/w description 15?14 00 rw upper two bits in counter not used. 13?0 0x0000 rw ptp real time clock in nanoseconds high?w ord [29:16] this is high?word of the ptp real time clock in nanoseconds. ptp real time clock in second s low ? w ord register (0x608 C 0x609): ptp_rtc_sl this register contains the ptp real time clock in seconds low?w ord. bit default r/w description 15?0 0x0000 rw ptp real time clock in seconds low? w ord [15:0] this is low?word of the ptp real - time clock in seconds. ptp real time clock in second s high ? w ord register (0x60a C 0x60b): ptp_rtc_sh this register contains the ptp real time clock in seconds high?word. bit default r/w description 15?0 0x0000 rw ptp r eal time clock in seconds high?w ord [31:16] this is high?word of the ptp real - time clock in seconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 244 revision 1.0 ptp real time clock in phase register (0x60c C 0x60d): ptp_rtc_phase this register indicates which sub phase of the ptp real time clock is current. the resolution is 8ns. the ptp real tim e clock is updated every 40ns. bit default r/w description 15?3 0x0000 ro reserved 2?0 000 rw ptp real time clock in sub - 8ns phase these bits indicate one of the 8ns sub?cycle times of the 40 ns period ptp real time clock. 000: 0ns (real time clock at the first 8ns cycle in 25mhz/40ns) 001: 8ns (real time clock at the second 8ns cycle in 25mhz/40ns) 010: 16ns (real time clock at the third 8ns cycle in 25mhz/40ns) 011: 24ns (real time clock at the fourth 8ns cycle in 25mhz/40ns) 100: 32ns (real time clock at the fifth 8ns cycle in 25mhz/40ns) 101?111: na this register is set to zero when e ver the ptp_r tc_nsl, ptp_rtc_nsh, ptp_rtc_sl, ptp_rtc_sh registers are written to by the cpu. 0x60e C 0x60f: reserved ptp rate in sub ? nanosecond s low ? w ord register (0x610 C 0x611): ptp_sns_rate_l this register contains the ptp rate control in sub?nanoseconds low?word . bit default r/w description 15?0 0x0000 rw ptp rate control in sub?nanoseconds low?word [15:0] this is low?word of ptp rate control value in units of 2 ? 32 ns. the ptp rate control value is used for incrementing (ptp_rate_dir = 0) or decrementing (ptp_rate_dir = 1) the frequen cy adjustment by the value in ptp_sns_rate_h [29:16] and ptp_sns_rate_l [15:0] per reference clock cycle (40ns). on each reference clock cycle, the ptp clock will be adjuste d ref_clk_period ptp_sns_rate_h/l value. setting both ptp_sns_rate_h/l registers value to 0x0 will disable both continuous and temporary adjustment modes. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 245 revision 1.0 ptp rate in sub ? nanosecond s high ? w ord and control register (0x612 C 0x613): ptp_sns_rate_h this register contains the ptp rate control in sub?nanoseconds high?word and configuration. bit default r/w description 15 0 rw rate direction control for temporary or continuous adjust ment mode (ptp_rate_dir) 1 = lower frequency. the ptp_sns_rate_h/l value will be added to system time clock on every 25mhz clock cycle. 0 = higher frequency. the ptp_sns_rate_h/l value will be subtracted from system time clock on every 25mhz clock cycle. 14 0 rw/sc (self clear) enable temporary adjustment mode for ptp 1588 clock (ptp_temp_adj_clk) 1 = enable the temporary incrementing (ptp_rate_dir = 0) or decrementing (ptp_rate_dir = 1) frequency adjustment by the value in the ptp_sns_rate_h/l registers over the duration of time set in the ptp_adj_dura_h/l registers on every 25mhz clock cycle. this bit is self cleared when the adjustment is completed. software can read this bit to check whether the adjustment is still in progress. 0 = disable the te mporary adjustment mode to the ptp clock. 13?0 0x0000 rw ptp rate c ontrol in sub?nanoseconds high?w ord [29:16] (ptp_sns_rate_h[29:16]) this is high?word of ptp rate control value in units of 2 C 32 ns. the ptp rate control value is used for incrementing (ptp_rate_dir = 0) or decrementing (ptp_rate_dir = 1) the fr equency adjustment by the value in ptp_sns_rate_h [29:16] and ptp_sns_rate_l [15:0] per reference clock cycle (40ns). on each reference clock cycle, the ptp clock wi ll be adjusted by a ref_clk_period ptp_sns_rate_h/l value. setting both ptp_sns_rate_h/l registers value to 0x0 will disable both continuous and temporary adjustment modes. ptp temporary adjustment mode duration in low ? wo rd register (0x614 C 0x615): ptp_temp_adj_dura_l this register contains the ptp temporary rate adjustment duration in low?word. bit default r/w description 15?0 0x0000 rw ptp temporary rate adjustment duration in low?word [15:0] this register is used to set the duration for the temporary rate adjustment in number of 25mhz c lock cycles. ptp temporary adjustment mode duration in high ? w ord register (0x616 C 0x617): ptp_temp_adj_dura_h this register contains the ptp temporary rate adjustment duration in high?word. bit default r/w description 15?0 0x0000 rw ptp temporary ra te adjustment duration in high?w ord [31:16] this register is used to set the duration for the temporary rate adjustment in number of 25mhz c lock cycles. 0x618 C 0x61f: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 246 revision 1.0 ptp message configuration 1 register (0x620 C 0x621): ptp_msg_cfg_1 this register contains the ptp message configuration 1. bit default r/w description 15?8 0x00 ro reserved 7 0 rw enable ieee 802. 1 as mode setting this bit will enable the ieee 802. 1as mode and all ptp packets are forwarded to port 3. 6 1 rw enable ieee 1588 ptp mode 1 = to enable the ieee 1588 ptp mode. 0 = to disable the ieee 1588 ptp mode. 5 0 rw enable detection of ieee 802.3 ethernet ptp message 1 = enable to detect the ethernet ptp message. 0 = disable to detect the ethernet ptp message. 4 1 rw enable detection of ipv4/udp ptp message 1 = enable to detect the ipv4/udp ptp message. 0 = disable to detect the ipv4/udp ptp message. 3 1 rw enable detection of ipv6/udp ptp message 1 = enable to detect the ipv6/udp ptp message. 0 = disable to detect the ipv6/udp ptp message. 2 0 rw selection of p2p or e2e 1 = select peer?to?peer (p2p) transparent clock mode. 0 = select end?to?end (e2e) transparent clock mode. 1 0 rw selection of master or slave 1 = select port 3 as master in ordinary clock mode. 0 = select port 3 as slave in ordinary clock mode. 0 1 rw selection of one?step or two?s tep operation 1 = select one?step clock mode. 0 = select two?step clock mode. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 247 revision 1.0 ptp message configuration 2 register (0x622 C 0x623): ptp_msg_cfg_2 this register contains the ptp message configuration 2. bit default r/w description 15?13 000 ro reserved 12 0 rw enable unicast ptp 1 = t he unicast ptp packet can be recognized. if the packet udp destination port is either 319 or 320 and the packet mac/ip address is not the ptp reserved address, then the packet will be considered as unicast ptp packet and the packet forwarding will be decided by regu lar table lookup. 0 = o nly multicast ptp packet s will be recognized. 11 0 rw enable alternate master 1 = a lternate master clock is supported. the sync , follow_up , delay _ req , and delay_resp messages of the same domain received at port 1/ port 2 by active master clock of same domain will be forwarded to port 1/ port 2. 0 = a lternate master clock is not supported. the sync message will not be forwarded to the other port when this bit = 0. the delay _ req message of same domain received at port 1/ port 2 by active master clock of same domain will be discarded on port 3 and be forwarded to port 2/ port 1 if delay _ req is for other domains. 10 1 rw ptp messages priority tx queue 1 = all ptp messages are assigned to highest priority tx queue. 0 = only the ptp event messages are assigned to highest priority tx queue. 9 0 rw enable checking of associated sync and follow_up ptp messages setting this bit will associate follow _ up message with sync message under certain situations. this bit only applie s to ptp frame s on port 3. refer to the micrel 1588 ptp developers guide document for detailed information on its usage. 8 0 rw enable checking of associated delay_req and delay_resp ptp messages while this bit is set, the delay _ resp message will be forwarded to port 1/port 2 if the associations do not match and is forwarded to port 3 if the associations match. setting this bit will associate d elay _r esp message with d elay _r eq message when it has the same domain, sequenceid, and sourcep ortid. the ptp frame will be forwarded to port 3 if the id matches. 7 0 rw enable checking of associated pdelay_req and pdelay_resp ptp messages setting this bit will associate pdelay_resp/pdelay_resp_follow_up messages with pdel ay_req message when they have the same domain, sequenceid, and sourceportid. the ptp frame will be forwarded to port 3 if the id matches. this bit only applie s to ptp frame s on port 3. 6 0 ro reserved 5 0 rw reserved 4 0 rw enable checking of domain field: domain_en setting this domain_en bit will enable the device to automatically check the domain field in ptp message with the ptp_domain_ver[7:0]. the ptp message will be forwarded to port 3 if the domain field is matched to ptp_domain_ver[7:0] otherwise the ptp message will be dropped. if set this bit to 0, regardless of domain field , the ptp messages a re forward ed to port 3 according to hardware default rules . 3 0 ro reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 248 revision 1.0 ptp message configuration 2 register (0x622 C 0x623): ptp_msg_cfg_2 (continued) bit def ault r/w description 2 1 rw enable the ipv4/udp checksum calculation for egress packets 1 = the device will re ? calculate and generate a 2 ? byte checksum value due to a frame contents change. 0 = the checksum field is set to zero. if the ipv4 /udp checksum is zero, the checksum will remain zero regardless of this bit setting. for ipv6 /udp, the checksum is always updated. 1 0 rw announce message from port 1 1 = the announce message is received from port 1 direction. 0 = the announce message is not received from port 1 direction. 0 0 rw announce message from port 2 1 = the announce message is received from port 2 direction. 0 = the announce message is not received from port 2 direction. ptp domain and version regist er (0x624 C 0x625): ptp_domain_ver this register contains the ptp domain and version information. bit default r/w description 15?12 0x0 ro reserved 11?8 0x2 rw ptp version this is the value of ptp message version number field. all ptp packets will be captured when th e receive ptp message version matches the value in this field. all ptp packets will be dropped if the receive ptp message version does not match the val ue in th is field . e xcept for the value of version 1, the device is always forwarding ptp packets between port 1 and port 2, and not to port 3. 7?0 0x00 rw ptp domain this is the value of ptp message domain number field. if the domain_en bit is set to 1 , the ptp messages will be filtered out and only forwarded to port 3 if the domain number matches . if the domain_en bit is set to 0 , the domain number field will be ignored under certain circumstances. 0x626 C 0x63f: reserved ptp port 1 receive latency reg ister (0x640 C 0x641): ptp_p1_rx_latency this register contains the ptp port 1 receive latency value in nanoseconds. bit default r/w description 15?0 0x019f rw ptp port 1 rx latency in nanoseconds [15:0] this register is used to set the fixed receive delay value from port 1 wire to rx timestamp reference point. the default value is 415ns. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 249 revision 1.0 ptp port 1 transmit latency register (0x642 C 0x643): ptp_p1_tx_latency this register contains the ptp port 1 transmit latency value in nanoseconds. bit default r/w description 15?0 0x002d rw ptp port 1 tx latency in nanoseconds [15:0] this register is used to set the fixed transmit delay value from port 1 tx timestamp reference point to wire. the default value is 45ns. ptp port 1 asymmetry correction register (0x644 C 0x645): ptp_p1_asym_cor this register contains the ptp port 1 asymmetry correction value in nanoseconds. bit default r/w description 15 0 rw ptp port 1 asymmetry correction sign bit 1 = the magnitude in bit[14:0] is negative. 0 = the magnitude in bit[14:0] is positive. 14?0 0x0000 rw ptp port 1 asymmetry correction in nanoseconds [14:0] this register is used to set the fixed asymmetry value to add in the correction field for ingr ess sync and pdelay_resp or to subtract from correction field for egress delay_req and pdelay_req. ptp port 1 link delay register (0x646 C 0x647): ptp_p1_link_ dly this register contains the ptp port 1 link delay in nanoseconds. bit default r/w description 15?0 0x0000 rw ptp port 1 link delay in nanoseconds [15:0] this register is used to set the link delay value between port 1 and link partner port. ptp port 1 egress timestamp low ? w ord register for pdelay_req and delay_req (0x648 C 0x649): p1_xdly_req_tsl this register contains the ptp port 1 egress timestamp low?word value for pdelay_req and delay_req frames in nanoseconds. bit default r/w description 15?0 0x0000 rw ptp port 1 egress timestamp for pdelay_req and delay_req in nanoseconds [15:0] this register contains port 1 egress timestamp low?word value for pdelay_req and delay_req frames in nanoseconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 250 revision 1.0 ptp port 1 egress timestamp high ? w ord register for pdelay_req and delay_req (0x64a C 0x64b): p1_xdly_req_tsh this register contains the ptp port 1 egress timestamp high?word value for pdelay_req and delay_req frames in nanoseconds. bit default r/w description 15?14 00 rw ptp port 1 egress timestamp for pdelay_req and delay_req in seconds [1:0] these bits are bits[ 1:0] of the port 1 egress timestamp value for pdelay_req and delay_req frames in seconds. 13?0 0x0000 rw ptp port 1 egress timestamp for pdelay_req and delay_req in nanoseconds [29:16] these bits are bits[ 29:16] of the port 1 egress timestamp value for pdelay_req and delay_req frames in nanoseconds. ptp port 1 egress timestamp low ? w ord register for sync (0x64c C 0x64d): p1_sync_tsl this register contains the ptp port 1 egress timestamp low?word value for sync frame in nanoseconds. bit default r/w description 15?0 0x0000 rw ptp port 1 egress timestamp for sync in nanoseconds [15:0] this register contains port 1 egress timestamp low?word value for sync frame in nanoseconds. ptp port 1 egress timestamp high ? w ord register for sync (0x64e C 0x64f): p1_sync_tsh this register contains the ptp port 1 egress timestamp high?word value for sync frame in nanoseconds. bit default r/w description 15?14 00 rw ptp port 1 egress timestamp for sync in seconds [1:0] these bits are bits[ 1:0] of the port 1 egress timestamp value for sync frame in seconds. 13?0 0x0000 rw ptp port 1 egress timestamp for sync in nanoseconds [29:16] these bits are bits[ 29:16] of the port 1 egress timestamp value for sync frame in nanoseconds. ptp port 1 egress timestamp low ? w ord register for pdelay_resp (0x650 C 0x651): p1_pdly_resp_tsl this register contains the ptp port 1 egress timestamp low?word value for pdelay_resp frame in nanoseconds. bit default r/w description 15?0 0x0000 rw ptp port 1 egress timestamp for pdelay_resp in nanoseconds [15:0] this register contains port 1 egress timestamp low?word value for pdelay_resp frame in nanoseconds. ptp port 1 egress timestamp high ? w ord register for pdelay_resp (0x652 C 0x653): p1_pdly_resp_tsh this register contains the ptp port 1 egress timestamp high?word value for pdelay_resp frame in nanoseconds. bit default r/w description 15?14 00 rw ptp port 1 egress timestamp for pdelay_resp in seconds [1:0] these bits are bits[ 1:0] of the port 1 egress timestamp value for pdelay_resp frame in seconds. 13?0 0x0000 rw ptp port 1 egress timestamp for pdelay_resp in nanoseconds [29:16] these bits are bits[ 29:16] of the port 1 egress timestamp high?word value for pdelay_resp frame in nanoseconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 251 revision 1.0 0x654 C 0x65f: reserved ptp port 2 receive latency register (0x660 C 0x661): ptp_p2_rx_latency this register contains the ptp port 2 receive latency value in nanoseconds. bit defa ult r/w description 15?0 0x019f rw ptp port 2 rx latency in nanoseconds [15:0] this register is used to set the fixed receive delay value from port 2 wire to rx timestamp reference point. the default value is 415ns. ptp port 2 transmit latency register (0x662 C 0x663): ptp_p2_tx_latency this register contains the ptp port 2 transmit latency value in nanoseconds. bit default r/w description 15?0 0x002d rw ptp port 2 tx latency in nanoseconds [15:0] this register is used to set the fixed transmit delay value from port 2 tx timestamp reference point to wire. the default value is 45ns. ptp port 2 asymmetry correction register (0x664 C 0x665): ptp_p2_asym_cor this register contains the ptp port 2 asymmetry correction value in nanoseconds. bit default r/w description 15 0 rw ptp port 2 asymmetry correction sign bit 1 = the magnitude in bit[14:0] is negative. 0 = the magnitude in bit[14:0] is positive. 14?0 0x0000 rw ptp port 2 asymmetry correction in nanoseconds [14:0] this register is used to set the fixed asymmetry value to add in the correction field for ingr ess sync and pdelay_resp or to subtract from correction field for egress delay_req and pdelay_req. ptp port 2 link delay regis ter (0x666 C 0x667): ptp_p2_link_dly this register contains the ptp port 2 link delay in nanoseconds. bit default r/w description 15?0 0x0000 rw ptp port 2 link delay in nanoseconds [15:0] this register is used to set the link delay value between port 2 and link partner port. ptp port 2 egress timestamp low ? word register for pdelay_req and delay_req (0x668 C 0x669): p2_xdly_req_tsl this register contains the ptp port 2 egress timestamp low?word value for pdelay_req and delay_req frames in nanoseconds. bit default r/w description 15?0 0x0000 rw ptp port 2 egress timestamp for pdelay_req and delay_req in nanoseconds [15:0] this register contains port 2 egress timestamp low?word value for pdelay _req and delay_req frames in nanoseconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 252 revision 1.0 ptp port 2 egress timestamp high ? word register for pdelay_req and delay_req (0x66a C 0x66b): p2_xdly_req_tsh this register contains the ptp port 2 egress timestamp high?word value for pdelay_req and delay_req frames in nanoseconds. bit default r/w description 15?14 00 rw ptp port 2 egress timestamp for pdelay_req and delay_req in seconds [1:0] these are bits[ 1:0] of the port 2 egress timestamp value for pdelay_req and delay_req frames in seconds. 13?0 0x0000 rw ptp port 2 egress timestamp for pdelay_req and delay_req in nanoseconds [29:16] these are bits[ 29:16] of the port 2 egress timestamp value for pdelay_req and delay_req frames in nanoseconds. ptp port 2 egress timestamp low ? word register for sync (0x66c C 0x66d): p2_sync_tsl this register contains the ptp port 2 egress timestamp low?word value for sync frame in nano seconds. bit default r/w description 15?0 0x0000 rw ptp port 2 egress timestamp for sync in nanoseconds [15:0] this register contains port 2 egress timestamp low?word value for sync frame in nanoseconds. ptp port 2 egress timestamp high ? word register for sync (0x66e C 0x66f): p2_sync_tsh this register contains the ptp port 2 egress timestamp high?word value for sync frame in nanoseconds. bit default r/w description 15?14 00 rw ptp port 2 egress timestamp for sync in seconds [1:0] these are bits[1:0] of the p ort 2 egress timestamp value for sync frame in seconds. 13?0 0x0000 rw ptp port 2 egress timestamp for sync nanoseconds [29:16] these are bits[ 29:16] of the port 2 egress timestamp value for sync frame in nanoseconds. ptp port 2 egress timestamp low ? word register for pdelay_resp (0x670 C 0x671): p2_pdly_resp_tsl this register contains the ptp port 2 egress timestamp low?word value for pdelay_resp frame in nanoseconds. bit default r/w description 15?0 0x0000 rw ptp port 2 egress timestamp for pdelay_resp in nanoseconds [15:0] this register contains port 2 egress timestamp low?word value for pdelay_resp frame in nanoseconds. ptp port 2 egress timestamp high ? word register for pdelay_resp (0x672 C 0x673): p2_pdly_resp_tsh this register contains the ptp port 2 egress timestamp high?word value for pdelay _resp frame in nanoseconds. bit default r/w description 15 C 14 00 rw ptp port 2 egress timestamp for pd elay _resp in seconds [1:0] these are bits[ 1:0] of the port 2 egress timestamp value for pdelay _resp frame in seconds. 13 ? 0 0x0000 rw ptp port 2 egress timestamp for sync nanoseconds [29:16] these are bits[ 29:16] of the port 2 egress timestamp value for pdelay _resp frame in nanoseconds. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 253 revision 1.0 0x674 C 0x67f: reserved gpio monitor register (0x680 C 0x681): gpio_monitor this register contains read?only access for the current values on gpio inputs. bit default r/w description 15?7 0x000 ro reserved 6?0 0x00 ro gpio inputs monitor this field reflects the current values s een on the gpio inputs. gpios 6 through 0 are mapped to bits[ 6 :0 ] in order. gpio output enable register (0x682 C 0x683): gpio_oen this register contains the control bits for gpio output enable. bit default r/w description 15?7 0x000 ro reserved 6?0 0x00 rw gpio output enable 0 = enables the gpio pin as trigger output. 1 = enables the gpio pin as timestamp input. gpios 6 through 0 are mapped to bits[ 6 :0 ] in order. 0x684 C 0x687: reserved ptp trigger unit interrupt status register (0x688 C 0x689): ptp_trig_is this register contains the interrupt status of ptp trigger output units. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 ro (w1c) trigger output unit interrupt status when this bit is set to 1, it indicates that the trigger output unit is done or has an er ror. the trigger output units from 12 to 1 are mapped to bit [11:0]. these 12 trigger output unit interrupt status bits are logical ored together and connected to i sr bit [10]. any of the interrup t status bits are cleared b y writing a 1 to the particular bit. ptp trigger unit interrupt enable register (0x68a C 0x68b): ptp_trig_ie this register contains the interrupt enable of ptp trigger output units. bit default r/w description 15?12 0x0 ro reserved 11?0 0x000 rw trigger output unit interrupt enable when this bit is set to 1, it indicates that the trigger output unit interrupt is enabled. the trigger output units from 12 to 1 are mapped to bit [11:0]. these 12 trigger output unit interrupt enables are logical ored together and connected to ier bit [10]. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 254 revision 1.0 ptp timestamp unit interrupt status register (0x68c C 0x68d): ptp_ts_is this register contains the interrupt status of ptp timestamp units. each bit in this regis ter is cleared by writing a 1 to it. bit default r/w description 15 0 ro (w1c) port 2 egress timestamp for pdelay_req/resp and delay_req frames interrupt statu s when this bit is set to 1, it indicates that the egress timestamp is available from port 2 for pdelay_req/resp and delay_req frames. this bit will be logical ored together with the rest of bits in this register and the logic al ored output is connected to isr bit [12]. 14 0 ro (w1c) port 2 egress timestamp for sync frame interrupt status when this bit is set to 1, it indicates that the egress timestamp is available from port 2 for sync frame. this bit will be logical ored together with the rest of bits in this register and t he logical ored output is connected to isr bit [12]. 13 0 ro (w1c) port 1 egress timestamp for pdelay_req/resp and delay_req frames interrupt statu s when this bit is set to 1, it indicates that the egress timestamp is available from port 1 for pdelay_req/resp and delay_req frames. this bit will be logical ored together with the rest of bits in this register and t he logical ored output is connected to isr bit [12]. 12 0 ro (w1c) port 1 egress timestamp for sync frame interrupt status when this bit is set to 1, it indicates that the egress timestamp is available from port 1 for sync frame. this bit will be logical ored together with the rest of bits in this register and t he logical ored output is connected to isr bit [12]. 11?0 0x000 ro (w1c) timestamp unit interrupt status when this bit is set to 1, it indicates that the timestamp unit is ready (ts_rdy = 1). the timestamp units from 12 to 1 are mapped to bit [11:0]. these 12 timestamp interrupts status are logical ored together with the rest of bits in this register and the logical ored output is con nected to isr bit [12]. ptp timestamp unit interrupt enable register (0x68e C 0x68f): ptp_ts_ie this register contains the interrupt enable of ptp timestamp units. bit default r/w description 15 0 rw port 2 egress timestamp for pdelay_req/resp and delay_req frames interrupt enab le when this bit is set to 1, it is enabled the interrupt when the egress timestamp is avai lable from port 2 for pdelay_req/resp and delay_req frames. this bit will be logical ored together with the rest of bits in this register and t he logical ored output is connected to ier bit [12]. 14 0 rw port 2 egress timestamp for sync frame interrupt enable when this bit is set to 1, it is enabled the interrupt when the egress timestamp is avai lable from port 2 for sync frame. this bit will be logical ored together with the rest of bits in this register and t he logical ored output is connected to ier bit [12]. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 255 revision 1.0 ptp timestamp unit interrupt enable register (0x68e C 0x68f): ptp_ts_ie (continued) 13 0 rw port 1 egress timestamp for pdelay_req/resp and delay_req frames interrupt enab le when this bit is set to 1, it is enabled the interrupt when the egress timestamp is avai lable from port 1 for pdelay_req/resp and delay_req frames. this bit will be logical ored together with the rest of bits in this register and the logical ored output is connected to ier bit [12]. 12 0 rw port 1 egress timestamp for sync frame interrupt enable when this bit is set to 1, it is enabled the interrupt when the egress timestamp is avai lable from port 1 for sync frame. this bit will be logical ored together with the rest of bits in this register and t he logical ored output is connected to ier bit [12]. 11?0 0x000 rw timestamp unit interrupt enable when this bit is set to 1, it indicates that the timestamp unit interrupt is enabled. the timestamp units from 12 to 1 are mapped to bit [11:0]. these 12 timestamp interrupts enable are logical ored together with the rest of bits in this regi ster and the logical ored output is connected to ier bit [12]. 0x690 C 0x733: reserved dsp control 1 register (0x734 C 0x735): dsp_cntrl_6 this register contains control bits for the dsp block. bit default r/w description 15?14 00 rw reserved 13 1 rw receiver adjustment set this bit to 1 when both ports 1 and 2 are in copper mode. when port 1 and/or port 2 is i n fiber mode, this bit should be cleared to 0. note that the fiber or copper mode is selected in the cfgr register (0x0d8 C 0x0d9). 12?0 0x1020 rw reserved 0x736 C 0x747: reserved analog control 1 register (0x748 C 0x749): ana_cntrl_1 this register contains control bits for the analog block. bit default r/w description 15?8 0x00 rw reserved 7 0 rw ldo off this bit is used to control the on/off state of the internal low - voltage regulator. 0 = ldo on (default) 1 = turn ldo off 6?0 0x00 rw reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 256 revision 1.0 analog control 3 register (0x74c C 0x74d): ana_cntrl_3 this register contains control bits for the analog block. bit default r/w description 15 0 rw hipls3 mask this bit must be set prior to initiating the linkmd function. 14 - 4 0x00 0 rw reserved 3 0 rw btrx reduce this bit must be set prior to initiating the linkmd function. 2 ? 0 000 rw reserved 0x74e C 0x7ff: reserved downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 257 revision 1.0 management information base (mib ) counters the ksz8462 provides 34 mib counters for each port. these counters are used to monitor the port activity for network management. the mib counters are formatted per port and all ports dropped packet as shown in table 24 . table 24 . format o f per - port mib counters bit name r/w description default 31 overflow ro 1 = counter overflow. 0 = no counter overflow. 0 30 count valid ro 1 = counter value is valid. 0 = counter value is not valid. 0 29?0 counter values ro counter value (read clear) 0x00000000 per -p ort mib counters are read using indirect memory access. the base address offsets and address ranges for all three ports are: ? port 1 base address is 0x00 and range is from 0x00 to 0x1f . ? port 2 base address is 0x20 and range is from 0x20 to 0x3f. ? port 3 base address is 0x40 and range is from 0x40 to 0x5f. per - port mib counters are read using indirect access control in the iacr register and the indirect access data registers in iadr4[15:0], iadr5[31:16] (0x02c C 0x02f ). the port 1 mib counters address memory offset as shown in table 25 . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 258 revision 1.0 table 25 . port 1 mib counters ? i ndirect memory offset offset counter name description 0x0 rxloprioritybyte rx lo ? priority (default) octet count including bad packets 0x1 rxhiprioritybyte rx hi ? priority octet count including bad packets 0x2 rxundersizepkt rx undersize packets w/ good crc 0x3 rxfragments rx fragment packets w/ bad crc, symbol errors or alignment errors 0x4 rxoversize rx oversize packets w/ good crc (max imum : 2000 bytes) 0x5 rxjabbers rx packets longer than 1522 bytes w/ either crc errors, alignment errors, or symbol errors (depends on max packet size setting) 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x8 rxalignmenterror rx packets within (64,1522) bytes w/ a non ? integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x9 rxcontrol8808pkts number of mac control frames received by a port with 88 ? 08h in ethertyp e field 0xa rxpausepkts number of pause frames received by a port. pause frame is qualified with etherty pe (88 ? 08h), da, control opcode (00 ? 01), data length (64b min), and a valid crc 0xb rxbroadcast rx good broadcast packets (not including error broadcast packets or valid multicast pa ckets) 0xc rxmulticast rx good multicast packets (not including mac control frames, error multicast packet s or valid broadcast packets) 0xd rxunicast rx good unicast packets 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length 0x11 rx256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length 0x13 rx1024to2000 octets total rx packets (bad packets included) that are between 1024 and 2000 octets in length (upper limit depends on max packet size setting) 0x14 txloprioritybyte tx lo ? priority good octet count, including pause packets 0x15 txhiprioritybyte tx hi ? priority g ood octet count, including pause packets 0x16 txlatecollision the number of times a collision is detected later than 512 bit ? times into the tx of a packet 0x17 txpausepkts number of pause frames transmitted by a port 0x18 txbroadcastpkts tx good broadcast packets (not including error broadcast or valid multicast packets) 0x19 txmulticastpkts tx good multicast packets (not including error multicast packets or valid broadcast packets) 0x1a txunicastpkts tx good unicast packets 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium 0x1c txtotalcollision tx total collision, half duplex only 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions 0x1e txsinglecollision successfully tx frames on a port for which tx is inhibited by exactly one collision 0x1f txmultiplecollision successfully tx frames on a port for which tx is inhibited by more than one collision downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 259 revision 1.0 table 26 . "all ports dropped packet" mib counter format bit default r/w description 30?16 ? n/a reserved 15?0 0x0000 ro counter value note : all ports dropped packet mib counters do not indicate overflow or v alidity; therefore, the application must keep track of overflow and valid conditions. all ports dropped packet mib counters are read using indirect memory access . the address offsets for these counters are shown in table 27 . table 27 . "all ports dropped packet" mib counters ? indirect memory offsets offset counter name description 0x100 port 1 tx drop packets tx packets dropped due to lack of resources 0x101 port 2 tx drop packets tx packets dropped due to lack of resources 0x102 port 3 tx drop packets tx packets dropped due to lack of resources 0x103 port 1 rx drop packets rx packets dropped due to lack of resources 0x104 port 2 rx drop packets rx packets dropped due to lack of resources 0x105 port 3 rx drop packets rx packets dropped due to lack of resources mib counter examples: 1. mib counter read (read port 1 rx64octets counter at indirect address offset 0x0e) write to reg. iacr with 0x1c0e (set indirect address and trigger a read mib counters operation) then : read reg. iadr5 (mib counter value [31:16]) // if bit [31] = 1, there was a counter overflow , // if bit [30] = 0, restart (re?read) from this register read reg. iadr4 (mib counter value [ 15:0 ]) 2. mib counter read (read port 2 rx64octets counter at indirect address offset 0x2e) write to reg. iacr with 0x1c2e (set indirect address and trigger a read mib counters operation) then : read reg. iadr5 (mib counter value [31:16]) // if bit [31] = 1, there was a counter overflow, // if bit [30] = 0, resta rt (re?read) from this register read reg. iadr4 (mib counter value [15:0]) 3. mib counter read (read port 1 tx drop packets counter at indirect address offset 0x100 ) write to reg. iacr with 0x1d00 (set indirect address and trigger a read mib counters operat ion) then : read reg. iadr4 (mib counter value [15:0]) additional mib information per port mib counters are designed as read clear. that is, these counters will be cleared af ter they are read. all ports dropped packet mib counters are not cleared after they are accessed. the applicat ion needs to keep track of overflow a nd valid conditions on these counters. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 260 revision 1.0 static mac address table the ksz8462 supports both a static and a dynamic mac address table. in respons e to a destination address (da) look up, the ksz8462 searches both tables to make a packet forwarding decision. i n response to a source address (sa) look up, only the dynamic table is searched for aging, migration and learning purposes. the static da look up result takes precedence over the dynamic da look up result. if there is a da match in both tables, the result from the static table is used. these entries in table 28 will not be aged out by the ksz8462. table 28 . static mac table format (8 entries) bit default value r/w description 57 ? 54 0000 rw fid filter vlan id ? identifies one of the 16 active vlans. 53 0 r/w use fid 1 = s pecifies the use of f id+mac for static table look up. 0 = s pecifies only the use of mac for static table look up. 52 0 r/w override 1 = o verrides the port setting transmit enable = 0 or receive enable = 0 setting. 0 = s pecifies no override . note: the override bit also allows usage (turns on the entry) even if the valid bit = 0. 51 0 r/w valid 1 = s pecifies that this entry is valid, and the look up result will be used . 0 = s pecifies that this entry is not valid . 50 ? 48 000 r/w forwarding p orts these 3 bits control the forwarding port(s): 000 = no forward . 001 = f orward to port 1. 010 = f orward to port 2. 100 = f orward to port 3. 011 = f orward to port 1 and port 2. 110 = f orward to port 2 and port 3. 101 = f orward to port 1 and port 3. 111 = broadcasting (excluding the ingress port) . 47 ? 0 0 r/w mac address 48 ? bit mac address downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 261 revision 1.0 static mac table lookup examples: 1. static address table read (read the second entry at indirect address offset 0x01) write to reg. iacr with 0x1001 (set indirect address and trigger a read static mac table oper ation) then: read reg. iadr3 (static mac table bits[ 57:48]) read reg. iadr2 (static mac table bits[ 47:32]) read reg. iadr5 (static mac table b its[ 31:16]) read reg. iadr4 (static mac table bits[ 15:0]) 2. static address table write (write the eighth entry at indirect address offset 0x07) write to reg. iadr3 (static mac table bits[ 57:48]) write to reg. iadr2 (static mac table bits[ 47:32]) write to reg. iadr5 (static mac table bits[ 31:16]) write to reg. iadr4 (static mac table bits[ 15:0]) write to reg. iacr with 0x0007 (set indirect address and trigger a write static mac t able operation) downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 262 revision 1.0 dynamic mac address table the dynamic mac a ddress (table 29) is a read only table. table 29 . dynamic mac address table format (1024 entries) bit default value r/w description 71 ro data not ready 1 = s pecifies that the entry is not ready, continue retrying until bit is set to 0. 0 = s pecifies that the entry is ready . 70 ? 67 ro reserved 66 1 ro mac empty 1 = s pecifies that there is no valid entry in the table 0 = s pecifies that there are valid entries in the table 65 ? 56 0x000 ro number of valid entries indicates how many valid entries in the table . 0x3ff means 1 k entries . 0x001 means 2 entries . 0x000 and bit [ 66 ] = 0 means 1 entry . 0x000 and bit [ 66 ] = 1 means 0 entry . 55 ? 54 ro timestamp specifies the 2 ? bit counter for internal aging. 53 ? 52 00 ro source port identifies the source port where fid+mac is learned: 00 = p ort 1 01 = p ort 2 10 = port 3 (host port) 51 ? 48 0x0 ro fid specifies the filter id. 47 ? 0 0x0000_0000_0000 ro mac address specifies the 48 ? bit mac a ddress. dynamic mac address lookup example: 1. dynamic mac address table read (read the first entry at indirect address offset 0 and retri eve the mac table size) write to reg. iacr with 0x1800 (set indirect address and trigger a read dynamic mac table operation) then: read reg. iadr1 (dynamic mac table bits[ 71:64]) // if bit [7 1] = 1, resta rt (re?read) from this register read reg. iadr3 (dynamic mac table bits[ 63:48]) read reg. iadr2 (dynamic mac table bits[ 47:32]) read reg. iadr5 (dynamic mac table bits[ 31:16]) read reg. iadr4 (dynamic mac table bits[ 15:0]) downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 263 revision 1.0 vlan table the ksz8462 uses the vlan table to perform lookups. if 802.1q vlan mode is enabled (sgc r2[15]), this table will be used to retrieve the vlan information that is associated with the ingress packet. th is information includes fid (f ilter id), vid (vlan id), and vlan membership as described in table 30 : table 30 . vlan table format (16 entries) bit default value r/w description 19 1 rw valid 1 = specifies that this entry is valid, the look up result will be used. 0 = specifies that this entry is not valid. 18?16 111 r/w membership specifies which ports are members of the vlan. if a da look up fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports sp ecified i n this field. for example: 101 means port 3 and port 1 are in this vlan. 15?12 0x0 r/w fid specifies the filter id. the ksz8462 supports 16 active vlans represented by these four bit fields. the fid is the mapped id. if 802.1q vlan is enabled, the look up will be based on fid+da and fid+sa. 11?0 0x001 r/w vid specifies the ieee 802.1q 12 bits vlan id. if 802.1q vlan mode is enabled, then ksz8462 will assign a vid to every ingress packet. if the packet is untagged or tagged with a null vid, then the packet is assigned with the default port vid of the ingress port. if the packet is tagged with non - null vid, then vid in the tag will be used. the look up process will start from the vlan table look up. if the vid is not valid, then packet will be dropped and no address learning will take place. if the vid is valid, then fid is retrieved. the fid+da an d fid+sa lookups are performed. the fid+da look up determines the forwarding ports. if fid+da f ails, then the packet will be broadcast to all the members (excluding the ingress port) of the vlan. if fid+sa fails, t hen the fid+sa will be learned. vlan table lookup examples: 1. vlan table read (read the third entry, at the indirect address offset 0x02) write to reg. iacr with 0x1402 (set indirect address and trigger a read vlan table operation) then : read reg. iadr5 (vlan table bits[ 19:16]) read reg. iadr4 (vlan table bits[ 15:0]) 2. vlan table write (write the seventh entry, at the indirect address offset 0x06) write to reg. iadr5 (vlan table bits[ 19:16]) write to reg. iadr4 (vlan table bits[ 15:0]) write to reg. iacr with 0x1406 (set indirect address and trigger a read vlan table operation) downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 264 revision 1.0 absolute maximum ratings ( 2 ) supply voltage (vdd_a3.3, vdd_io) ......... C 0.5v to + 5 .0v supply voltage (vdd_al, vdd_l) .............. C 0.5v to +1.8v input voltage (all inputs) .............................. C 0.5v to + 5 .0v output voltage (all outputs) ........................ C 0.5v to + 5 .0v lead temperature (soldering, 20s) ............................ 260c storage temperature (t s ) ......................... C 65c to +150c m aximum junction temperature (t j ) ....................... +125c hbm esd rating ........................................................... 2kv operating ratings ( 3 ) supply voltage vdd_a3.3 ...................................... +3.1 35 v to +3. 465v vdd_l, vdd_al , vdd_col .............. +1.25v to +1.4v vdd_io (3.3v) ............................... +3.1 35 v to +3. 465v vdd_io (2.5v) ............................... +2.3 7 5v to +2.6 2 5v vdd_io (1.8v) ................................... +1.7 1 v to +1. 8 9v ambient operating temperature (t a ) industrial (hli/fhli) ............................. ?40c to +85c thermal resistance (4) junction?to?ambient ( ja ) ................................ . 49 c/w junction?to?case ( jc ) ..................................... 19c/w electrical characteristics ( 5 ) symbol condition parameter/symbol min . typ . max . units supply current for 100base?tx operation (internal low - voltage regulator on , vdd_ a3.3 = 3.3v, vdd_io = 3.3v) (4) 100% traffic on both p orts i vdd_a3.3 42 ma i vdd_io 87 pdiss device 428 mw link, no traffic on both p orts , eee feature is off i vdd_a3.3 41 ma i vdd_io 86 pdiss device 421 mw ports 1 and 2 powered down (p1cr4, p2cr4 bit[11] = 1) i vdd_a3.3 4 .6 ma i vdd_io 70 pdiss device 246 mw ports 1 and 2 not connected, using edpd feature (pmctrl bits[1:0] = 01) i vdd_a3.3 5.4 ma i vdd_io 70 pdiss device 249 mw ports 1 and 2 linked, no traffic, using eee feature i vdd_a3.3 5.3 ma i vdd_io 71 pdiss device 251 mw soft power -d own mode (pmctrl bits[1:0] = 10) i vdd_a3.3 0.98 ma i vdd_io 2.0 pdiss device 10 mw notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. unused inputs must always be ti ed to an appropriate logic voltage level (ground to vdd_io). 3. no heat spreader (hs) in this package. the jc / ja is under air velocity 0m/s. 4. i vdd_a3.3 measured at pin 9. i vdd_io measured at pins 21, 30, and 56. i vdd_al measured at pin s 6 and 16 . i vdd_dl measured at pins 4 0 and 5 1. 5. t a = 25c. specific ation for packaged product only. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 265 revision 1.0 electrical characteristics ( 5 ) (continued) symbol condition parameter/symbol min. typ. max. units hardware power -d own mode while the pwdrn pin (pin 17) is held low. i vdd_a3.3 0.18 ma i vdd_io 0 pdiss device 0.6 mw supply current for 100base - tx operation ( internal low voltage regulator off; vdd_ a3.3 and vdd_io = 3.3v ; vdd_l, vdd_al and vdd_col = 1.4 v) (4) 100% traffic on both ports i vdd_a3.3 40 ma i vdd_io 0.6 i vdd_al + i vdd_dl 88 pdiss device 258 mw link, no traffic on both ports, eee feature is off. i vdd_a3.3 40 ma i vdd_io 0.7 i vdd_al + i vdd_dl 87 pdiss device 256 mw ports 1 and 2 powered down (p1cr4, p2cr4 bit[11] = 1) i vdd_a3.3 3.8 ma i vdd_io 0.5 i vdd_al + i vdd_dl 71 pdiss device 114 mw ports 1 and 2 not connected, using edpd feature (pmctrl bits[1:0] = 01) i vdd_a3.3 4.5 ma i vdd_io 0.6 i vdd_al + i vdd_dl 72 pdiss device 117 mw ports 1 and 2 linked, no traffic, using eee feature i vdd_a3.3 5.2 ma i vdd_io 0.7 i vdd_al + i vdd_dl 74 pdiss device 123 mw soft powerdown mode (pmctrl bits[1:0] = 10) i vdd_a3.3 0.2 ma i vdd_io 0.7 i vdd_al + i vdd_dl 1.1 pdiss device 4.3 mw hardware powerdown mode while the pwdrn pin (pin 17) is held low. i vdd_a3.3 0.2 ma i vdd_io 0.7 i vdd_al + i vdd_dl 0.1 pdiss device 4.1 mw downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 266 revision 1.0 electrical characteristics ( 5 ) (continued) symbol condition parameter/symbol min typ . max units supply current for 10base?t operation (internal low voltage regulator on; vdd_a3.3 = 3.3v, vdd_io = 3.3v) (4) 100% traffic on both ports i vdd_a3.3 53 ma i vdd_io 74 pdiss device 417 mw link, no traffic on both ports i vdd_a3.3 17 ma i vdd_io 71 pdiss device 290 mw supply current for 10base - t operation (internal low voltage regulator off; vdd_a3.3 and vdd_io = 3.3v; vdd_l, vd d_al and vdd_col = 1.4v) (4) 100% traffic on both ports i vdd_a3.3 51 ma i vdd_io 0.5 i vdd_al + i vdd_dl 76 pdiss device 277 mw link, no traffic on both ports i vdd_a3.3 16 ma i vdd_io 0.6 i vdd_al + i vdd_dl 74 pdiss device 158 mw internal voltage regulator output voltage v ldo output voltage at vdd_l vdd_io = 2.5v or 3.3v; internal regulator enabled; measured at pins 40 and 51 1.32 v cmos inputs (vdd_io = 3.3v/2.5v/1.8v) v ih input high voltage 2.1/1.7 /1.3 v v il input low voltage 0.9/0.9 /0.6 v i in input current v in = gnd ~ vdd_io ?10 10 a x1 crystal/osc input pin v ih input high voltage vdd_a3.3 = 3.3v, vdd_io = any 2.1 v v il input low voltage vdd_a3.3 = 3.3v, vdd_io = any 0.9 v i in input current 10 a pwrdn input v ih input high voltage vdd_a3.3 = 3.3v, vdd_io = any 1 .1 v v il input low voltage vdd_a3.3 = 3.3v, vdd_io = any 0. 3 v fxsd input v ih input high voltage vdd_a3.3 = 3.3v, vdd_io = any 2 .1 v v il input low voltage vdd_a3.3 = 3.3v, vdd_io = any 1.2 v downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 267 revision 1.0 electrical characteristics ( 5 ) (continued) symbol condition parameter/symbol min typ. max units cmos outputs (vdd_io = 3.3v/2.5v/1.8v) v oh output high voltage i oh = ?8ma 2.4/1.9 /1.5 v v ol output low voltage i ol = 8ma 0.4/0.4 /0.2 v |i oz | output tri?s tate leakage 10 a 100 base - tx transmit ( measured differentially after 1:1 t ransformer ) v o peak differential output voltage 100 ? termination on the differential output 0.95 1.05 v v imb output voltage imbalance 100 ? termination on the differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty - cycle distortion 0.25 ns overshoot 5 % v set reference voltage of i set 0.65 v output jitter peak?to?peak 0.7 1.4 ns 10 base - t receive v sq squelch threshold 5mhz square wave 400 mv 10 base - t transmit (measured differentially after 1:1 t ransformer) vp peak differential output voltage 100 ? termination on the differential output 2.2 2.5 2.8 v jitter added 100 ? terminati on on the differential output (p eak?to?peak) 1.8 3.5 ns t r , t f rise/fall time 25 ns led outputs i led output drive current each led pin (p1/2led0, p1/2led1) 8 ma i/o pin internal pull -u p and pull -d own effective resistance r1.8pu i/o pin effectiv e pull - up resistance vdd_io = 1.8v 57 100 187 k? r1.8pd i/o pin effective pull - down resistance 55 100 190 r2.5pu i/o pin effective pull - up resistance vdd_io = 2.5v 37 59 102 k? r2.5pd i/o pin effective pull - down resistance 35 60 110 r3.3pu i/o pin effective pull - up resistance vdd_io = 3.3v 29 43 70 k? r3.3pd i/o pin effective pull - down resistance 27 43 76 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 268 revision 1.0 timing specifications host interface read / write timing figure 22 . host interface read/write t iming table 31 . host interface read/write timing parameters symbol description min . typ . max . unit t 1 csn, cmd valid to rdn, wrn active 0 ns t 2 rdn active to read data sd[15:0] valid note: this is the sd output delay after rdn becomes active until valid read data is available . 24 32 ns t 3 rdn inactive to read data invalid note: the processor latches valid read data at the rising edge of rdn . 1 2 ns t 4 csn, cmd hold time after rdn, wrn inactive 0 ns t 5 wrn active to write data valid (bit [12] = 0 in rxfdpr) 8 16 ns wrn active to write data valid (bit [12] = 1 in rxfdpr) note: it is better if the processor can provide data in less than 4ns after wrn is active. if the processor provides data more than 4ns after wrn is active, make sure that rxfdpr bit [ 12 ] = 0. 4 ns t 6 rdn read active time (low) 40 ns wrn write active time (low) 40 ns t 7 rdn read inactive time (high) 10 ns wrn write inactive time (high) 10 ns downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 269 revision 1.0 auto?negotiation timing figure 23 . auto - negotiation timing table 32 . auto - negotiation timing parameters timing parameter description min . typ . max . unit t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulses per burst 17 33 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 270 revision 1.0 trigger output unit and timestamp input unit timing figure 26 provides details and constraints on various timing relationships within the twelve trigger output units and the timestamp input units. figure 24 . trigger output unit and timestamp input unit timing downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 271 revision 1.0 table 33 . trigger output unit and timestamp input unit timing parameters timing parameter description min. typ. max. unit trigger output unit timing [cascade mode} t casp1 in cascade mode for trigx_cfg_1[6:4] = 100, or 101, or 110 (neg. edge, pos. edge, & shift reg. output signals). minimum time between start of one tou and the start of another tou cascaded on the same gpio pin. 80 ns t casp2 in cascade mode for trigx_cfg_1[6:4] = 010, 011, 100, or 101 (neg. pulse, pos. pulse, neg. periodic, and pos. periodic output signals). minimum time between start of one tou and the start of another tou cascaded on the same gpio pin. 120 ns t cyccasp in cascade mode for trigx_cfg_1[6:4] = 010, & 011 (neg. pulse , pos. pulse output signals). in cascade mode, the cycle time of the trigger output unit operating in the indicated modes. 80 32 + p width2 ns t cycnc1 in cascade mode for trigx_cfg_1[6:4] = 100 or 101 (neg. periodic , pos. periodic output signals). minimum cycle time for any trigger output unit operating in the indicated modes. 80 32 + p width2 ns t gap23 in cascade mode for trigx_cfg_1[6:4] = 010, & 011 (neg. pulse , pos. pulse output signals ). minimum gap time required between end of period of first trigger output unit to beginning of output of 2nd trigger output unit . 80 ns p width2 in cascade mode, the minimum low or high pulse width of the trigger output unit. 8 ns trigger output unit timing [non - cascade mode] t cycnc2 in non - cascade mode , the minimum cycle time for any trigger output unit. 80 32 + p width1 ns t pogap in non - cascade mode, the minimum time between the end of the generated pulse to the start of the next pulse. 32 ns p width1 in non - cascade mode, the minimum low or high pulse width of the trigger output unit. 8 ns timestamp input unit timing ip high allowable high time of an incoming digital waveform on any gpio pin 24 - - ns ip low in non - cascade mode, the minimum time between the end of the generated pulse to the start of the next pulse. 24 - - ns ip cyc in non - cascade mode, the minimum time between the end of the generated pulse to the start of the next pulse. 48 - - ns downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 272 revision 1.0 serial eeprom interface timing figure 25 . serial eeprom timing table 34 . serial eeprom timing parameters timing parameter description min . typ . max . unit fscl eesk clock frequency 2.5 mhz t1 setup time for start bit 33 ns t2 hold time for start bit 33 ns t3 hold time for data 20 ns t4 setup time for data 33 ns t5 output valid time for data 60 ns t6 setup time for stop bit 33 ns t7 hold time for stop bit 33 ns downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 273 revision 1.0 reset timing and power sequencing the ksz8462 reset timing requirement is summarized in figure 26 and table 35 . figure 26 . ksz8462 reset and power sequence timing table 35 . reset timing parameters ( 6 , 7 , 8 ) timing parameter description min . max . unit tvr supply voltages rise time (mu st be monotonic) 0 s tsr stable supply voltages to de - assertion of reset 10 ms tcs strap- in pin configuration setup time 5 ns tch strap- in pin configuration hold time 5 ns trc de - assertion of reset to strap - in pin output 6 ns notes 6. the recommended powering sequence is to bring up all voltages at the same time. however, if that ca nnot be attained, then a recommended power - up sequence is to have the transceiver (vdd_a3.3) and digital i/os (vdd_io) voltages power up before the low - volta ge core (vdd_al, vdd_l, and vdd_col) voltage, if an external low voltage core supply is used. there is no power sequence requirem ent between transceiver (vdd_a3.3) and digital i/os (vdd_io) power rails. the power - up waveforms should be monotonic for all supply voltages to the ksz8462. 7. after the de - assertion of reset, it is recommended to wait a minimum of 100s before starting programming of the device through any interface. 8. the recommended power - down sequence is to have the low - voltage core voltage power - down first before powering down the transceiver and digital i/o voltages. downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 274 revision 1.0 reset circuit guidelines figure 27 is the recommended reset circuit for powering up the ksz8462 device if reset is triggere d by the power supply. figure 27 . sample reset circuit figure 28 is the recommended reset circuit for applications where reset is driven by another device (e. g., cpu or fpga). at power?on?reset, r, c and d1 provide the neces sary ramp rise time to reset the ksz8462 device. the rst_out_n from cpu/fpga provides the warm reset after power up. figure 28 . recommended reset circuit for interfacing with a cpu/fpga reset output downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 275 revision 1.0 reference circuits C led strap-in pins the pull?up and pull?down reference circuits for the p1led0/h816 and p2led0/leb e strapping pins are shown in figure 29 . the supply voltage for the leds must be at least ~2.2v, depending on the particular led and the load resistor. if vdd_io is 1.8v, then a different (higher voltage) supply must be used for the leds. figure 29 . typical led strap- in circuit downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 276 revision 1.0 reference clock C connection and selection figure 30 shows a crystal or external clock source, such as an oscillator, as the reference c lock for the ksz8462. the reference clock is 25mhz for all operating modes of the ksz8462. if an oscill ator is used, connect it to x1, and leave x2 unconnected. the resistor shown on x2 is optional and can be used to reduce the current to the crystal if needed, depending on the specific crystal that is used. the maximum recommended resistor value is 30. figu re 30 . 25 mhz crystal and oscillator clock connection option s selection of reference crystal table 36 . typical reference crystal characteristics characteristics value units frequency 25 mhz frequency tolerance (maximum) 50 ppm e ffective series resistance (maximum) 50 ? downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 277 revision 1.0 selection of isolation transformers a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common?mode choke is recommended for exceeding fcc requirements. table 38 gives recommended transformer characteristics. table 37 . transformer selection criteria parameter value test condition turns ratio 1 ct : 1 ct open?circuit inductance ( maximum ) 350 h 100mv, 100khz, 8ma leakage inductance ( maximum ) 0.4 h 1mhz (min) inter?winding capacitance ( maximum ) 12pf d.c. resistance ( maximum ) 0.9 ? insertion loss ( maximum ) ?1.0db 100khz C 100mhz hipot ( maximum ) 1500vrms table 38 . qualified single port magnetic magnetic manufacturer part number auto mdi?x number of port pulse h1102 nl yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 bel fuse s558?5999?u7 yes 1 delta lf8505 yes 1 lankom lf?h41s yes 1 tdk (mag jack) tla?6t718 yes 1 downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 278 revision 1.0 package information ( 9 ) and recommended landing pattern 64 -pin 10mm 10mm lqfp note: 9. package information is correct as of the publication date. for updates and most current inf ormation, go to www.micrel.com . downloaded from: http:///
micrel, inc. ksz8462hl/ksz8462fhl june 11, 2014 279 revision 1.0 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its us e. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/ or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat ent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appl iances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are device s or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to res ult in a significant injury to the user. a pur chasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 14 micrel, incorporated. downloaded from: http:///

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